Design Verification Engineer - Internal IP

Delos; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving medical benefits

Housing subsidy of $2k per month

Relocation support

Daily lunch + dinner in office

Job summary

A leading technology company in Austin is looking for a Design Verification Engineer to enhance custom IPs for cutting-edge technologies. This position requires expertise in UVM and SystemVerilog, strong debugging skills, and collaboration with engineers on design functionality. Candidates should have experience in verifying digital designs and will enjoy benefits including comprehensive medical coverage and housing assistance. Expect some travel to the San Jose office for collaboration.

Qualifications

• Proficiency with UVM and SystemVerilog is essential.
• Ability to debug complex digital designs.
• Solid knowledge of computer architecture fundamentals.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches.
• Define and execute verification plans for functional correctness.
• Work closely with architects and designers on validation.

Skills

Proficiency with UVM

SystemVerilog

Strong debugging skills

Knowledge of computer architecture

Tools

Python

Perl

TCL

Job description

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
• Debug complex datapath and protocol issues in RTL and testbench environments.
• Work closely with architects and designers to validate functionality and design intent.
• Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
• Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

You may be a good fit if you have

• Proficiency with UVM and SystemVerilog.
• Strong debugging and problem-solving skills for complex digital designs.
• Solid knowledge of computer architecture and digital design fundamentals.
• Hands‑on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Strong candidates may also have experience with

• Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
• Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.