Design Verification Engineer - ASIC & SystemVerilog (UVM)

Amazon; Austin (TX); On-site; USD 109,700 - 160,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced verification engineer to define and implement digital chip SOCs for LEO satellite communications. You will work on state-of-the-art verification environments, test plans, and regressions, collaborating with design and systems teams to validate ASICs using Verilog/SystemVerilog and UVM.

You will contribute to automated regression frameworks and data organization while leveraging Matlab models and SystemC/C to ensure robust

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or Computer Science, or related field, or equivalent experience.
• 2+ years in verification, preferably in communication systems.
• 2+ years in UVM.
• Master's or Ph.D degree in Electrical/Communications Engineering.
• 3+ years in digital verification, preferably in communication systems.
• Familiarity with Matlab.
• Modem design verification experience.
• SystemC, C or Matlab model : development or DV integration experience.
• Familiarity with formal verification techniques.
• Strong written and verbal skills.

Responsibilities

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM.
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Skills

Verification experience

UVM experience

Education

Bachelor's degree in EE/CE/CS

Master's or PhD in EE/CE

Tools

SystemC

C/C++

Matlab

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking an experienced verification engineer to define and implement digital chip SOCs for LEO satellite communications. You will work on state-of-the-art verification environments, test plans, and regressions, collaborating with design and systems teams to validate ASICs using Verilog/SystemVerilog and UVM.

You will contribute to automated regression frameworks and data organization while leveraging Matlab models and SystemC/C to ensure robust