Design Verification Architect

Intel; Santa Clara (CA); Hybrid; USD 164,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Job summary

Intel in California seeks a seasoned verification architect to define verification strategy for pre-silicon design, architect testbenches, and develop UVM or formal verification methods. You will integrate block testbenches in chip-level environments and verify integration across teams.

The role emphasizes test strategy development, collaboration with analog/digital teams, and supporting post-silicon validation activities in a hybrid work model.

Qualifications

• Bachelor's degree with 10+ years of industry experience or Master's with 8+ years.
• 8+ years of experience with IP/SoC pre-silicon validation and SystemVerilog coding.
• Experience with hardware simulation tools and methodologies (VCS/Verdi).
• Experience with UVM methodology.

Responsibilities

• Define, architect, and document verification strategy for pre-silicon design.
• Architect testbenches and develop UVM or formal verification approaches.
• Integrate block testbenches in chip-level UVM environments and verify integration.
• Develop test strategy, testbench architecture, and test plans to meet specs.
• Enable interaction with analog and digital teams and support post-silicon validation.

Skills

SystemVerilog

UVM

Pre-silicon validation

Hardware simulation

IP/SoC management

Education

Bachelor's or Master's in related field

Tools

VCS

Verdi

Job description

Position Overview

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the pre-silicon design in the most optimal manner. Architects testbenches and develops Universal Verification Methodology (UVM) or formal-based verification approaches. Integrates block testbenches in chip-level UVM environments and verifies integration.

Job Details

Job Description:

Key Responsibilities

• Define, architect, and document verification strategy and methodologies for implementing and verifying pre-silicon design in the most optimal manner
• Architect testbenches and develop Universal Verification Methodology (UVM) or formal-based verification approaches
• Integrate block testbenches in chip-level UVM environments and verify integration
• Develop test strategy, testbench architecture, and test plans for design blocks to conform to specifications
• Enable interaction with analog and digital teams and support post-silicon validation activities
• Collaborate with architecture and design teams to create random test generation plans, run functional simulations to identify gaps in design specifications, and conduct failure analysis, coverage analysis, and closure
• Define and develop the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage

You should demonstrate the following professional traits to be successful

• Collaborative and communicative, with the ability to work across diverse teams and mentor junior engineers
• Strong problem-solving skills with disciplined execution and a proactive mindset
• Results-driven, with the ability to drive optimal solutions between analog and digital designs

Qualifications

Minimum Qualifications

Bachelor's degree with 10+ years of relevant industry experience, or a Master's degree in a related field with 8+ years of relevant industry experience

You must have 8+ years of experience with/in:

• IP/SoC pre-silicon validation and coding using SystemVerilog
• Hardware simulation tools and methodologies (VCS/Verdi)
• IP environment and configuration management tools
• UVM methodology

Preferred Qualifications

• Demonstrated ability to debug complex logic designs and validate system-level functionality
• DDR design domain knowledge with strong understanding of DFI/DDR/LPDDR protocols
• Experience with VSCode, GitHub Copilot, or any other AI-assisted development tools
• Experience to Formal Property Verification and Git version control

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Folsom

Additional Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00 - 232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.