Design For Test (DTF) Engineer

Eastridge Workforce Solutions; San Diego (CA); On-site; USD 208,000 - 270,000; Full time

Job summary

Eastridge Workforce Solutions is seeking an experienced Design-for-Test (DFT) Engineer in San Diego, CA. The role focuses on implementing DFT methodologies for RF, Bluetooth, and WLAN chipsets, working closely with Front-End and Physical Design teams.

A minimum of 5+ years DFT experience, MBIST and Tessent flow expertise, and scripting skills are required. The position is a contract, full-time role with expected hands-on support for memory BIST, ATPG, and scan compression, plus VTRAN pattern

Qualifications

• 5+ years of hands-on DFT experience.
• MBIST experience with Siemens Tessent Flow.
• Experience with ATPG and Tetramax.
• Experience with scan compression (SEQ/Ultra/TestKompress).
• Gate-level simulation and debugging experience.
• Verilog/SystemVerilog RTL experience.
• Scripting/automation with Tcl, Perl, Python.

Responsibilities

• Implement DFT methodologies for advanced semiconductor designs.
• Develop MBIST using Siemens Tessent Flow.
• Perform gate-level simulations and debug failures.
• Implement scan compression using SEQ, Ultra, or TestKompress.
• Develop ATPG using Tetramax.
• Support ATPG diagnosis and ATE debug.
• Translate DFT patterns using VTRAN.
• Create automation/scripts with Tcl/Perl/Python.
• Work with RTL in Verilog/SystemVerilog.
• Assist timing/constraints with PrimeTime.
• Collaborate with Front-End, Physical Design and Test teams.
• Troubleshoot complex DFT and silicon test issues.

Skills

DFT experience

Memory BIST

ATPG

Gate-level simulation

Verilog/SystemVerilog RTL

Scripting (Tcl/Perl/Python)

Scan compression (SEQ/Ultra/TestKomP)

VTRAN pattern translation

Tools

Siemens Tessent Flow

Tetramax

PrimeTime

VTRAN

Job description

• Perform DFT pattern translation using VTRAN.

Location: San Diego, CA

Schedule: Full-Time

Employment Type: Contract

Pay Rate: $100-$130/hr

Position Overview

We are seeking an experienced Design-for-Test (DFT) Engineer to support the development and validation of next-generation semiconductor products. This role will work closely with Front-End Design and Physical Design teams to implement DFT methodologies and test solutions supporting advanced RF, Bluetooth, and Wireless LAN (WLAN) chipsets.

The ideal candidate will have 5+ years of hands-on DFT experience with strong knowledge of memory BIST, ATPG, scan compression, gate-level simulation, and silicon bring-up.

Responsibilities

• Implement and support Design-for-Test (DFT) methodologies for advanced semiconductor designs.
• Develop and implement Memory BIST (MBIST) using Siemens Tessent Flow.
• Perform gate-level simulations and debug simulation failures.
• Implement and support scan compression using SEQ, Ultra, and/or TestKompress.
• Develop and execute ATPG using Tetramax.
• Perform ATPG diagnosis and support ATE debug and silicon bring-up.
• Perform DFT pattern translation using VTRAN.
• Develop automation and scripting solutions using Tcl, Perl, and/or Python.
• Work with RTL designs using Verilog and SystemVerilog.
• Support static timing analysis and timing-related activities using PrimeTime.
• Work with CDC, clock-gating checks, and timing constraints.
• Collaborate closely with Front-End, Physical Design, Verification, and Test Engineering teams.
• Troubleshoot complex DFT and silicon test issues independently.

Required Qualifications

• 5+ years of relevant industry DFT experience.
• Hands-on experience with Memory BIST (MBIST) and Siemens Tessent Flow.
• Experience with ATPG and Tetramax.
• Experience with scan compression, including SEQ, Ultra, and/or TestKompress.
• Strong experience with gate-level simulation and debugging.
• Experience with Verilog/SystemVerilog RTL.
• Experience with scripting and automation using Tcl, Perl, and/or Python.
• Strong problem-solving and debugging skills.
• Ability to independently manage and complete technical assignments.

Preferred Qualifications

• Experience with ATPG diagnosis, ATE debug, and silicon bring-up.
• Experience with VTRAN pattern translation.
• Familiarity with PrimeTime, STA, CDC, clock-gating checks, and timing constraints.
• Previous experience supporting RF, Bluetooth, WLAN, or other wireless semiconductor products.

Benefits

Eastridge Workforce Solutions offers the following benefits, subject to applicable eligibility requirements . Use this link https://applicantcenterstorage.blob.core.windows.net/public-documents/EWSb1cb390e-729b-47eb-ab2f-b92adafbdd07-2024EplicaBenefitSummaryTempExternal.pdf to learn more about benefits available to Eastridge's temporary employees. Due to the varying length(s) of temporary assignments, Eastridge Workforce Solutions' Temporary Staff are not eligible for paid time off , unless required by applicable state law in which the position is based . However, from time to time Eastridge's clients may offer additional benefits to Eastridge employees while on assignment. Information about those benefits will be communicated when applicable.

Disclaimer

The compensation and benefits information in this posting represents Eastridge's good faith and reasonable estimate of what it might pay for this position. Eastridge reserves the right to modify this information at any time, subject to applicable law.

Equal Opportunity Employer

Eastridge Workforce Solutions is an Equal Opportunity Employer. We provide an inclusive work environment that celebrates diversity , and all qualified candidates receive consideration for employment without regard to race, color, sex, sexual orientation, gender identity , gender e xpression, religion, national origin, age (40 and over), disability, military status, genetic information or any other basis protected by applicable federal, state, or local laws. Eastridge Workforce Solutions also prohibits harassment or retaliation of applicants or employees based on any of these protected categories. It is our policy to comply with all applicable federal, state and local laws respecting consideration of unemployment status in making hiring decisions. Please note that Eastridge is unable to provide visa sponsorship to applicants.

Background Checks

Certain clients require Eastridge Workforce Solutions to perform background check s. Eastridge will consider qualified applicants with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds, including but not limited to the California Fair Chance Act, the Los Angeles City Fair Chance Ordinance, Los Angeles County Fair Chance Ordinance for Employers, and the San Francisco Fair Chance Ordinance.

Massachusetts Candidates

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

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Eastridge's Pre-Use Notice of Collection and Automated Decision-Making Technologies : https://www.eastridge.com/data-collection-notice .

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