Design Automation Engineer - Neuromorphic Computing - Intel Corporation

OpenTalent; Hillsboro (OR); On-site; USD 130,000 - 170,000; Full time

Job summary

OpenTalent is seeking an experienced engineer to enhance and maintain the ASIC tool flow for Loihi projects in Hillsboro, Oregon. You will contribute design automation, regression tests, and automated utilities to support RTL, verification, and physical design teams.

The role emphasizes scripting in Perl/Python/TCL, SystemVerilog/OOP programming, and experience with large FPGA platforms such as HAPS or ZeBu. Remote work is not advertised.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field required.

Responsibilities

• Enhance and maintain Loihi's ASIC tool flow by implementing design automation algorithms, software tools, utilities, and regression tests.
• Support RTL designers, verification engineers and physical design engineers by providing automated solutions to meet KPIs.
• Enable early software development by setting up a scalable framework mapping silicon designs in simulation and emulation.
• Write custom scripts to manipulate synthesis and physical design tools for efficient, low-power/high-performance designs.

Skills

ASIC tool flows

Python

Perl

TCL

SystemVerilog

OO Programming

Education

Bachelors or Masters in EE/CS

Tools

HAPS

ZeBu

Job description

Job Details:

Job Description:

• Enhance and maintain Loihi's asynchronous EDA tool flow by implementing design automation algorithms, software tools, utilities, and regression tests.
• Support RTL designers, verification engineers and physical design engineers by providing automated solutions to achieve product quality and target KPIs.
• Enable early SW development by setting up a scalable framework mapping silicon designs in simulation and emulation.
• Write custom scripts to manipulate synthesis and physical design tools for low power/high performance custom designs.

Qualifications:

• Bachelors and 4+ years OR Masters and 2+ years of experience in developing and deploying production quality tools, flows and methods for silicon design.
• 4+ years of experience in developing and maintaining the entire ASIC tool suite. E.g. synthesis, place and route, ATPG, FEV, RV, STA, LVS/DRC.
• 4+ years of experience with scripting languages such as Perl, TCL, Python, etc.
• 2+ years of experience in delivering multiple silicon tape-outs.
• Strong System-Verilog/System-C/Object Oriented Programming background.
• Experience with large scale FPGA platforms like HAPS and/or emulation frameworks like ZeBu.
• 1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement:

Position of Trust