Custom Timing and Verification CAD Engineer

Apple, Inc.; Jackson (TN); On-site; USD 185,000 - 325,000; Full time

Benefits offered by this job

Stock programs

Employee stock purchase plan

Medical and dental coverage

Retirement benefits

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in the United States seeks an entry-level engineer for its Custom Timing CAD team, focusing on transistor-level timing verification and formal verification. You will learn flows, develop automation, and collaborate with circuit designers across programs to enable clean sign-off.

You will work with NanoTime, ESP, PrimeTime, and HSPICE, contributing to methodology and tool improvements within Apple’s advanced chip design environment.

Qualifications

• BS degree in Electrical/Computer Engineering or related field.
• Strong programming or scripting in Perl, Python, TCL, or similar.
• Solid understanding of digital or custom IC design at transistor level.

Responsibilities

• Develop, maintain, and improve CAD flows and automation scripts.
• Support timing and verification runs, interpret results, and resolve issues.
• Drive timing and formal verification closure with circuit designers.
• Contribute to methodology documentation and guidelines.
• Engage with EDA vendors to report issues and drive tool improvements
• Build automation to scale support across programs.

Skills

Programming/scripting in Perl, Python,

Digital/Custom IC design understanding

Noise/Timing debugging

Cross-functional collaboration

Flow ownership and methodology

Education

BS degree in Electrical Engineering/Computer Engineering/CS

Tools

NanoTime

ESP

PrimeTime

HSPICE

DSPF/SPF formats

SystemVerilog RTL

RTL-to-schematic checking

Job description

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom Timing CAD team builds and owns the flows, tools, and methodologies that make that verification possible. We are looking for an entry-level engineer who is eager to learn, technically curious, and excited to work at the intersection of circuit design and CAD engineering.

Description

In this role, you will support and develop flows for two of the most critical sign‑off disciplines in custom IC design - transistor-level timing verification using NanoTime and formal verification using ESP. You will partner closely with analog and digital designers across multiple programs and technology nodes, helping them set up flows, debug issues, and achieve clean sign‑off. The work you do will directly shape the quality and schedule of Apple's most advanced chips.

Responsibilities

• Develop, maintain, and improve CAD flows and automation scripts for NanoTime and ESP
• Support design teams in setting up timing and verification runs, interpreting results, and resolving tool and methodology issues
• Drive timing and formal verification closure in collaboration with circuit designers
• Contribute to methodology documentation and guidelines adopted across programs and design organizations
• Engage with EDA vendors to report issues, evaluate new features, and drive tool improvements
• Build automation to improve flow efficiency, reduce runtime, and scale support across concurrent programs

Preferred Qualifications

• Hands‑on experience with transistor-level timing and formal verification tools such as NanoTime, ESP, PrimeTime, or HSPICE, including flow ownership and methodology development
• In‑depth knowledge of dynamic logic, memory arrays, or mixed‑signal circuit techniques, and ability to debug complex timing and verification issues independently
• Experience with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF in the context of timing sign‑off
• Experience with formal verification methodologies and SystemVerilog RTL, including RTL‑to‑schematic equivalence checking
• Track record of driving cross‑functional collaboration with design, layout, and EDA vendor teams to resolve tool and methodology issues
• Experience developing or contributing to organization‑wide CAD methodology documentation and best practices
• Familiarity with AI/ML‑driven CAD workflows and interest in applying GenAI techniques to flow automation and timing analysis
• Strong communicator with the ability to present technical work clearly to both peers and management, and drive issues to resolution across teams

Minimum Qualifications

• Minimum of BS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field + 10 years relevant industry experience
• Strong programming or scripting experience in Perl, Python, TCL, or similar language
• Solid understanding of digital or custom IC design at transistor level and static timing analysis

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $184,700 and $324,800, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.