CPU SoC Verification Engineer

Google; San Diego (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google seeks a CPU SoC DV Engineer to ensure functional integrity from RTL simulation to silicon characterization. You will build robust verification environments, drive GLS, and collaborate with ATE teams to debug high-speed patterns in production.

You will translate simulation-based sequences into ATE-ready formats, perform timing-annotated simulations, and contribute to scalable verification workflows. This role emphasizes performance, efficiency, and hardware integration at Google.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 4 years of ARM-based SoC verification experience including cache coherency and NoC interconnects.
• Experience with post-silicon debug across PVT corners and RTL/GLS workflows.

Responsibilities

• Drive ARM SoC and sub-system verification, simulation, and debug for CPU RTL and gate-level nets.
• Lead post-silicon debug to diagnose hardware failures and ensure pattern stability in production.
• Translate simulation sequences into ATE/SLT formats for high-fidelity testing.
• Execute GLS and timing-annotated simulations with standard EDA tools.
• Generate ATE patterns using virtual tester environments for accurate translation.

Skills

ARM-based SoC verification

RTL verification

GLS workflows

Post-silicon debug

PVT corner debugging

NoC interconnects

Education

Bachelor's degree in Electrical Engineering/Computer Engineering/Computer Science or equivalent

Master's degree or PhD (preferred)

Tools

UVM/OVM methodologies

Python

Perl

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: San Diego, CA, USA; Mountain View, CA, USA.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.
• Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.
• Experience in RTL verification and Gate Level Simulation (GLS) workflows.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will develop robust verification environments, drive GLS, and partner with ATE teams to debug and stabilize high-speed patterns in a production environment.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
• Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
• Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
• Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
• Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .