Compiler Backend Engineer

Normal Computing Corp.; United States; Presencial; USD 150.000 - 230.000; Jornada completa

Descripción de la vacante

Normal Computing Corp. is building memory-bound AI inference hardware and a compiler stack to map models efficiently. As a Backend Compiler Engineer, you design and implement code generation, scheduling, and memory planning for our custom accelerator.

You will work at the boundary of compiler and hardware, validate against simulators and FPGA prototypes, and help bring up silicon while balancing abstraction and performance.

Formación

• Seasoned in compiler optimizations for accelerators or non-CPU targets.
• Experience turning high-level IR into device-executable code.
• Familiar with memory-bound, data-centric workloads and scheduling.

Responsabilidades

• Develop passes to map lowered programs to hardware code.
• Own scheduling and memory placement across resources for latency reduction.
• Decide fusion/dispatch strategies to minimize data movement.
• Collaborate with hardware architects to feed compiler constraints.
• Maintain performance regression suites and validate with simulators, FPGA prototypes, and silicon.

Conocimientos

Compiler optimization

Code generation

Scheduling

Memory planning

Python

C/C++

Rust

PyTorch compilation stack

Hardware awareness

Herramientas

TorchDynamo

FX

Inductor

torch.export

IREE

TVM

XLA

LLVM

MLIR

Descripción del empleo

• Normal’s hardware runs the most memory-bound parts of large-model inference inside memory itself, rather than shuttling weights to a processor. The software that makes this programmable doesn’t exist yet in any standard form. Getting a model correct on that hardware is the frontend’s job; making it fast is yours
• Our hardware does not look like a CPU or GPU, so its compiler backend can’t be borrowed from one. As a Compiler Engineer focused on the backend, you will help design and build the custom compilation that maps LLM inference onto it, from scheduling and memory planning to the code our hardware actually executes
• You will work at the boundary between the compiler and the hardware, closely enough to know when an optimization belongs at a different layer, or when the right answer is a new abstraction. Our chip is pre-silicon, so you will measure your work against our simulators and FPGA prototypes first, and against silicon as it arrives
• Code Generation: Build the passes that turn lowered programs into the code our hardware executes, designing new compilation approaches where conventional ones don’t fit. Success means correct, efficient code for every operation our models need
• Scheduling and Memory Planning: Own how work and data are scheduled and placed across our hardware’s resources, measured by utilization and end-to-end latency on LLM inference
• Fusion and Dispatch: Own fusion and dispatch decisions for LLM inference, so the hardware spends its time computing rather than moving data
• Hardware Co-Design: Work the abstraction layer between the compiler and the hardware, and feed compiler constraints back to our hardware architects while the design can still change
• Profiling and Validation: Validate every optimization with measured results from simulators, FPGA prototypes, and then silicon, and maintain a performance regression suite the team trusts
• Cross-Team Handoffs: Take lowered programs from our frontend compiler engineers, and decide with the team which operations the compiler generates and which use hand-tuned kernels

Comfort working close to hardware: you think in terms of memory bandwidth and utilization as well as asymptotic complexityDeep experience with compiler optimization or code generation for accelerators or other non-CPU targets: scheduling, tiling, fusion, or resource allocationTrack record of shipping optimizations that moved a measured performance numberComfort building software for hardware that is still evolving, from simulation through bring-upWillingness to design compilation approaches from first principles when existing ones don’t fit the hardwareFluency in Python, and familiarity with C, C++, or RustExperience with PyTorch’s compilation stack (TorchDynamo, FX, Inductor, torch.export) or other ML compilers, such as IREE, TVM, or XLAExperience compiling for in-memory, spatial, or other non-von-Neumann compute targetsContributions to open-source compiler or kernel infrastructure (e.g., PyTorch, Triton, TVM, MLIR, LLVM)Background in hardware design tools such as logic synthesis or place-and-routeExperience building or using cycle-level or performance simulators to guide optimization decisionsPublishing or presenting compiler or performance work at venues such as MLSys, ASPLOS, or CGO