Backend Compiler Engineer for AI Inference Hardware

Normal Computing Corp.; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Normal Computing in Mountain View seeks a Compiler Engineer focused on the backend to map LLM inference onto custom hardware. You will design and build the compilation flows, from scheduling and memory planning to the code the hardware executes.

You will work at the boundary between compiler and hardware, measuring progress with simulators and FPGA prototypes, then silicon, and collaborate with the frontend team and hardware architects to push performance and reduce data movement.

Qualifications

• Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets: scheduling, tiling, fusion, or resource allocation.
• Comfort working close to hardware: memory bandwidth and utilization matter as well as asymptotic complexity.
• Willingness to design compilation approaches from first principles when existing ones don't fit the hardware.
• Track record of shipping optimizations that moved measurable performance numbers.
• Comfort building software for hardware that is still evolving, from simulation through bring-up.
• Fluency in Python, and familiarity with C, C++, or Rust.

Responsibilities

• Code Generation: Build passes turning lowered programs into hardware-executable code.
• Scheduling and Memory Planning: Optimize work and data placement for low latency.
• Fusion and Dispatch: Decide fusion/dispatch for efficient computation.
• Hardware Co-Design: Define constraints between compiler and hardware architects.
• Profiling and Validation: Validate optimizations with simulators, FPGA prototypes, and silicon.
• Cross-Team Handoffs: Coordinate with frontend engineers on which ops are generated vs. hand-tuned.

Skills

Compiler optimization

Code generation

Scheduling

Memory planning

Python

C/C++/Rust

Job description

Normal Computing in Mountain View seeks a Compiler Engineer focused on the backend to map LLM inference onto custom hardware. You will design and build the compilation flows, from scheduling and memory planning to the code the hardware executes.

You will work at the boundary between compiler and hardware, measuring progress with simulators and FPGA prototypes, then silicon, and collaborate with the frontend team and hardware architects to push performance and reduce data movement.