Coherent Memory System Architect, Silicon

Google; Mountain View (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google seeks a Coherent Memory System Architect to innovate in silicon solutions for their consumer products. The ideal candidate will have extensive experience in micro-architecture and ASIC design, leading efforts to develop high-performance memory systems.

Qualifications

• 8 years of experience in the micro-architecture and ASIC design.
• Experience with CPU, GPU and memory system design.
• Knowledge in Coherent Interconnects and memory systems.

Responsibilities

• Explore design choices for memory systems.
• Analyze performance and power trade-offs.
• Collaborate with hardware design and validation teams.

Skills

Micro-architecture

Design of ASIC blocks

Register-Transfer Level (RTL)

Performance analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree or PhD in related field

Tools

Hardware Description Languages (HDL)

Job description

Coherent Memory System Architect, Silicon

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Coherent Memory System Architect, Silicon

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in micro-architecture and design of ASIC blocks.
• Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks: Central Processing Units (CPUs), Graphics Processing Units (GPUs), Caches, Memory Management Units (MMUs) or Coherent Fabrics.
• Experience in micro-architecture/design performance analysis, tools, and simulators.
  
  

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in micro-architecture and design of ASIC blocks.
• Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks: Central Processing Units (CPUs), Graphics Processing Units (GPUs), Caches, Memory Management Units (MMUs) or Coherent Fabrics.
• Experience in micro-architecture/design performance analysis, tools, and simulators.
  
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in building build time configurable designs.
• Knowledge in one or more of these areas, Coherent Interconnects, Caches, Memory Systems.
• Knowledge of Hardware Description Languages (HDL) such as System verilog, Verilog.
  
  

About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will shape the future of our coherent memory systems for consumer SoCs. You will leverage your deep technical expertise in design and uArch to create the most advanced power and performance efficient mobile coherent systems. Your work will have a direct impact on the performance, efficiency, and innovation of our next-generation devices. You will work with hardware designers and validation teams to build and test the best hardware architectures. As part of this work, you will participate in the development of technology in the memory system and filing associated patents.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Explore and evaluate different uArch and design choices for power and performance efficient coherent and non-coherent memory systems.
• Author hardware uArch specification for next-generation coherent/non-coherent memory systems.
• Analyze performance and power trade-offs.
• Work with Hardware design, verification, emulation and validation teams to build and test the hardware architecture.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Seniority level

• Seniority level

  Not Applicable

Employment type

• Employment type

  Full-time

Job function

• Job function

  Other, Information Technology, and Engineering

• Industries

  Information Services and Technology, Information and Internet

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