Gate-level Noise (Signal Integrity) / STA CAD Engineer

Apple, Inc.; Sunnyvale (CA); In loco; USD 129.000 - 195.000; Tempo pieno

Vantaggi offerti da questo lavoro

Stock programs

Discretionary RSU awards

Employee Stock Purchase Plan

Medical and dental coverage

Educational expense reimbursement

Relocation support

Descrizione del lavoro

Apple is seeking a Gate-level Noise (Signal Integrity) / STA CAD Engineer to support gate-level glitch noise and STA methodologies ensuring signal integrity for Apple silicon across technology nodes.

You’ll learn sign-off methodologies, margin models, and production CAD flows while collaborating with CAD and physical design teams on noise and timing constraints, ECO tasks, and automation including AI-agent workflows.

Competenze

• BS in Electrical Engineering, Computer Engineering, or related technical discipline.
• 1-2 years of experience in CAD methodology, EDA support, or digital design.
• Foundational understanding of gate-level signal integrity concepts, including crosstalk glitch noise and static timing analysis (STA).
• Exposure to industry-standard SI and STA tools (e.g., PrimeTime-SI, Tempus, or equivalent) through coursework, internship, or self-study.
• Basic scripting skills in Python, Tcl, and/or Perl.
• Willingness to learn noise and timing sign-off and ECO concepts with team support.
• Ability to execute well-defined tasks with close guidance and mentorship.
• Coursework or project exposure to standard cell library noise characterization (e.g., CCSN) or SPICE simulation basics.
• Familiarity with place-and-route (P&R) concepts and physical design flow basics.
• Curiosity about AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.
• Good communication skills and eagerness to learn.

Mansioni

• Assist with applying established sign-off methodologies, noise margins, and tool qualification procedures for gate-level glitch noise and static timing analysis (STA), under senior engineer guidance.
• Run and maintain existing production CAD flows and scripts for core noise and STA tools, supporting constraint setup through tapeout sign-off.
• Help execute glitch noise analysis tasks - including checking glitch thresholds and propagation reports under supervision.
• Assist with root-cause analysis of crosstalk glitch and timing anomalies, learning to use established automated triage workflows and AI-agent pipelines.
• Work closely with design and physical design teams on noise/timing constraints and flow issues, escalating closure and waiver decisions to senior engineers.
• Help execute noise and timing ECO tasks to support design convergence toward tapeout.
• Participate in tool and version qualification activities, helping track QoR and performance data against golden baselines.
• Help maintain documentation and learn noise and STA best practices from the team.

Conoscenze

CAD methodology

EDA support

Digital design

Gate-level SI concepts

Python scripting

Tcl scripting

Perl scripting

AI/LLM workflows

Formazione

BS in Electrical/Computer Engineering

Strumenti

PrimeTime-SI

Tempus

Descrizione del lavoro

Gate-level Noise (Signal Integrity) / STA CAD Engineer

Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it! As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.

Description

In this role, your primary responsibilities will include: Assist with applying established sign-off methodologies, noise margins, and tool qualification procedures for gate-level glitch noise and static timing analysis (STA), under senior engineer guidance. Run and maintain existing production CAD flows and scripts for core noise and STA tools, supporting constraint setup through tapeout sign-off. Help execute glitch noise analysis tasks - including checking glitch thresholds and propagation reports under supervision. Assist with root-cause analysis of crosstalk glitch and timing anomalies, learning to use established automated triage workflows and AI-agent pipelines. Work closely with design and physical design teams on noise/timing constraints and flow issues, escalating closure and waiver decisions to senior engineers. Help execute noise and timing ECO tasks to support design convergence toward tapeout. Participate in tool and version qualification activities, helping track QoR and performance data against golden baselines. Help maintain documentation and learn noise and STA best practices from the team.

Minimum Qualifications

• BS in Electrical Engineering, Computer Engineering, or related technical discipline.

Preferred Qualifications

• 1-2 years of experience in CAD methodology, EDA support, or digital design.
• Foundational understanding of gate-level signal integrity concepts, including crosstalk glitch noise and static timing analysis (STA).
• Exposure to industry-standard SI and STA tools (e.g., PrimeTime-SI, Tempus, or equivalent) through coursework, internship, or self-study.
• Basic scripting skills in Python, Tcl, and/or Perl.
• Willingness to learn noise and timing sign-off and ECO concepts with team support.
• Ability to execute well-defined tasks with close guidance and mentorship.
• Coursework or project exposure to standard cell library noise characterization (e.g., CCSN) or SPICE simulation basics.
• Familiarity with place-and-route (P&R) concepts and physical design flow basics.
• Curiosity about AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.
• Good communication skills and eagerness to learn.

Compensation & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs.

Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan.

You will also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Equal Opportunity & Diversity

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Accessibility

At Apple, we believe accessibility is a fundamental human right. You will find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple's workplace

Learn about reasonable accommodations for job applicants

Application Process

Apple accepts applications to this posting on an ongoing basis.