CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple Inc.; Austin (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

An established industry player is seeking a CAD Engineer to join their Silicon Technologies group. In this role, you will develop and maintain gate-level static timing analysis flows, ensuring that cutting-edge processors and system-on-chip designs meet performance and efficiency standards. You will collaborate with design teams to troubleshoot timing issues and drive methodology improvements, all while working closely with EDA vendors to incorporate innovative solutions. If you have a passion for tackling complex challenges and a desire to contribute to the technology that powers beloved devices, this opportunity is for you.

Qualifications

• 3+ years of experience in static timing analysis and gate-level flows.
• Familiarity with Python, Tcl, and high-performance SoC designs.

Responsibilities

• Develop and enhance gate-level STA flows for silicon designs.
• Analyze timing paths and debug issues related to timing constraints.

Skills

Static Timing Analysis

Python

Tcl

Communication Skills

Problem Solving

Education

Bachelor's Degree

Tools

STA Tools

Job description

CAD Engineer - Timing for Gate-Level Flows & Methodologies

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!

Description

As a member of our STA CAD team, you will:

1. Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
2. Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
3. Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
4. Develop and maintain scripts and methods for timing analysis and power reduction
5. Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
6. Analyze timing paths to identify key issues, including post-silicon timing debug
7. Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems

Minimum Qualifications

• Minimum requirement of BS and 3+ years of relevant industry experience

Preferred Qualifications

• Experience with static timing analysis tools and flows
• Understanding of programming fundamentals and concepts. Familiarity with Python and Tcl or other high level programming languages
• Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
• Understanding of fundamentals in noise, cross-talk, variation and timing margins
• Knowledge of timing/SDC constraints, hands on experience in creation/validation a plus
• Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.