CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple Inc.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

An innovative company is seeking a CAD Engineer to join their Silicon Technologies group. In this role, you will design and enhance gate-level static timing analysis flows for high-performance processors, ensuring that devices operate seamlessly. Your expertise will directly contribute to the efficiency and performance of cutting-edge technology, enabling millions to enjoy their devices. If you are passionate about solving complex challenges and thrive in a collaborative environment, this opportunity is perfect for you. Join a team that values detail and creativity in crafting next-generation solutions.

Qualifications

• 10+ years of relevant industry experience in CAD and timing analysis.
• Expertise in static timing analysis tools and methodologies.

Responsibilities

• Develop and enhance gate-level STA flows for silicon designs.
• Analyze timing paths and debug issues related to timing closure.

Skills

Static Timing Analysis

Python Programming

Tcl Programming

Timing Closure

Debugging Skills

Communication Skills

Education

Bachelor's Degree in Engineering

Tools

STA Tools

Job description

CAD Engineer - Timing for Gate-Level Flows & Methodologies

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices!

Description

As a member of our STA CAD team, you will:

• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
• Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
• Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
• Develop and maintain scripts and methods for timing analysis and power reduction
• Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
• Analyze timing paths to identify key issues, including post-silicon timing debug
• Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems

Minimum Qualifications

• Minimum requirement of BS and 10+ years of relevant industry experience

Preferred Qualifications

• Expert power user of static timing analysis tools and flows
• Advanced programming skills with Python and Tcl or other high level programming languages
• Proven track record of development and deployment of complex CAD flows and automation
• Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
• Deep understanding of noise, cross-talk, variation, margins, and timing models
• Knowledge of timing/SDC constraints, hands on experience in creation and validation of constraints
• Excellent communicator who can accurately assess and describe issues to management as well as follow solutions through to completion

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.