CAD and PPA Methodology Engineer

MaC VC

San Diego (CA)

On-site

USD 170,000 - 254,000

Full time

5 days ago
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Job summary

Qualcomm Technologies, Inc. seeks a GPU/ASIC engineer to advance power, performance, and area for state-of-the-art GPU cores. You will work across RTL-to-GDSII, formal verification, and ECO generation, interacting with design, technology, and post-silicon teams.

The role requires strong RTL/SV skills, experience with Synopsys tools, and scripting ability. Collaboration, initiative, and deliverable quality are essential.

Qualifications

  • Bachelor's/Master's/PhD in a related field with relevant work experience.
  • Experience with RTL to GDSII flows and ASIC design life cycles.
  • Strong scripting in UNIX shell, Python, Perl or TCL.

Responsibilities

  • Develop and optimize flows/methodologies for PPA improvements.
  • Collaborate with design, tech, power, and sign-off teams.
  • Drive RTL-to-GDSII delivery and ECO fixes with timing constraints.

Skills

Verilog
SystemVerilog
RTL design
RTL synthesis
PPA optimization
Clock Tree Analysis
ECO methods

Education

Bachelor's degree in Computer Engineering/Computer Science/Electrical Engineering
Master's degree in Computer Engineering/Computer Science/Electrical Engineering
PhD in Computer Engineering/Computer Science/Electrical Engineering

Tools

Synopsys Fusion Compiler
Synopsys RTL-Architect
PrimePower
PrimeTime
Prime Closure

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary

As a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation and verification. They will collaborate with multiple functional teams including design, technology, power, implementation, sign-off and post-silicon to drive PPA improvements into GPU cores.

Knowledge and experience in the following is a definite advantage
  • Implementation and delivery of GPU cores from RTL to GDSII
  • Semi-custom design flow and methodology development
  • Identifying areas for flow and process improvements
  • Verilog and System-Verilog languages
  • RTL synthesis using physically aware tools
  • Design constraint management for power, timing, clocking, interfaces
  • Formal Verification for RTL-netlist and netlist-netlist checks
  • Clock Tree Analysis and Optimization
  • ECO methods for functional and timing fixes
  • Managing design goals and tradeoffs in power, performance, and area
Preferred Qualifications
  • At-least 5-7 years of experience developing methodologies for PPA improvement
  • Basic understanding of digital design and RTL development
  • Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure
  • Script writing experience in UNIX shell, Python, Perl and/or TCL
  • Excellent interpersonal and analytical skills as well as ability to work independently
  • Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented
Minimum Qualifications
  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
  • Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
  • PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay Range And Other Compensation & Benefits

$169,500.00 - $254,300.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

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