ASIC Verification Engineer

Broadcom; San Jose (CA); On-site; USD 119,000 - 190,000; Full time

Job summary

An established industry player is seeking a skilled verification engineer to join their dynamic team. This role involves functional verification of sophisticated designs, focusing on external interfacing IPs and memory controllers. You will be responsible for all aspects of verification, from test planning to execution and coverage closure. The ideal candidate will have extensive experience with verification methodologies, particularly UVM, and a strong understanding of SystemVerilog assertions. Join a forward-thinking company that values innovation and offers a competitive benefits package, including medical, dental, and 401(K) matching.

Benefits

Medical, dental, and vision plans

401(K) participation with company matching

Employee Stock Purchase Program (ESPP)

Paid sick leave

Vacation time

Company-paid holidays

Employee Assistance Program (EAP)

Qualifications

• 8+ years of experience in functional verification and test planning.
• Strong expertise in architecting reusable test benches.

Responsibilities

• Conduct functional verification of complex designs and memory controllers.
• Develop test plans, execute tests, and ensure coverage closure.

Skills

SystemVerilog

UVM

ARM-based bus protocols (APB, AXI, CHI)

Functional verification

Test bench development

Verilog

Education

Bachelor's Degree

Master's Degree

Job description

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Job Description:

Job duties:

• Functional verification of complex designs, especially external interfacing IPs/memory controllers.
• Responsible for all aspects of verification from test planning, test bench development, test execution, and functional/code coverage closure.

Skills/Expertise:

• Expertise in architecting reusable and constrained random test benches from scratch.
• Expertise in verification methodologies like UVM.
• Verification expertise with Interface IP designs. Beneficial areas include High bandwidth memory (HBM) PHY / controller sub-systems, Ethernet/PCIe/CXL (Physical coding sublayer)/Serdes designs.
• Experience with ARM-based bus protocols like APB, AXI, and CHI is highly desirable.
• Strong understanding of SystemVerilog assertions and the ability to quickly write effective coverage and assertion properties. Ability to understand Verilog designs and develop relevant verification properties.

Minimum Industry Experience:

• Bachelor's Degree + 8+ years of related experience; OR
• Master's Degree + 6+ years of experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $119,000 - $190,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental, and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside the USA, please be sure to fill out a home address as this will be used for future correspondence.