ASIC uArchitecture & Design Engineer

Nokia; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading company is seeking a digital hardware engineer to design and optimize RTL code for complex ASIC components. The role involves collaborating with architecture and verification teams to deliver high-performance designs. Candidates should possess strong Verilog skills and experience with simulation tools, ensuring designs meet stringent performance and power requirements.

Qualifications

• Strong proficiency in Verilog for digital circuit design.
• Experience with simulation tools like Verdi, VCS, or Questa.
• Familiarity with timing analysis and tools for optimization.

Responsibilities

• Design, implement, and optimize RTL code for ASIC components.
• Collaborate with teams to translate specifications into Verilog code.
• Perform timing analysis to ensure design meets constraints.

Skills

Verilog

Simulation tools

Timing analysis

Optimization techniques

Job description

Applied R&D (AR) consists of target-oriented research either with the goal of solving a particular problem / answering a specific question or for multi-discipline design, development, and implementation of hardware, software, and systems including maintenance support. Supplies techno-economic consulting to clients. AR work is characterised by its detailed and complex nature in order to systematically combine existing knowledge and practices to further developing and incrementally improving products, operational processes, and customer-specific feature development.

Digital Hardware (DHA) comprises the specification, design, and implementation of digital hardware (baseband hardware) while applying design targets such as low cost, high yield, and high reliability. Digital boards are high density boards with numerous components including high speed connections and high precision reference clocks. DHA requires analogue design knowhow and simulation capabilities.

Qualifications

Required Qualifications:

• Strong proficiency in Verilog for digital circuit design and RTL coding.
• Experience with simulation tools like Verdi, VCS, or Questa to debug and verify RTL designs.
• Familiarity with timing analysis and ensuring timing closure for complex designs.
• Experience with tools and optimization techniques for area, timing, and power.

Other Preferred Qualifications:

• Experience with IP integration, including integrating third-party or pre-designed IP cores into larger RTL systems.
• Experience with multi-core processor designs, interconnect systems, and complex system-level designs.
• Experience with physical design and an understanding of the constraints that affect layout, power, and performance.
  
  

Responsibilities

Key Responsibilities:

• Design, implement, and optimize RTL code for complex ASIC components using Verilog/System Verilog, including processors, memory subsystems, and high-speed interfaces.
• Develop modular and reusable RTL code that meets functional, performance, and power requirements.
• Work closely with architecture, design, and verification teams to understand system-level specifications and translate them into efficient, scalable Verilog code.
• Integrate and optimize pre-existing IP blocks (e.g., CPU cores, memory controllers) into the RTL design, ensuring proper functionality and performance.
• Perform timing analysis and ensure the RTL design meets the required timing constraints for high-performance and low-power operation.
• Use simulation tools (e.g., Verdi, VCS, Questa) to verify RTL functionality and identify and resolve bugs during the development cycle.
• Run synthesis and place-and-route tools to convert RTL code to gate-level designs and ensure that the synthesized design meets the performance, area, and power targets.
• Collaborate with cross-functional teams to address design challenges and optimize RTL code for performance, area, and power.
• Document and communicate design decisions, progress, and results.