ASIC Static Timing and Synthesis Engineers (00005)

22nd Century Technologies Inc.; Baltimore (MD); On-site; USD 90,000 - 120,000; Full time

Job summary

22nd Century Technologies Inc. is seeking an experienced ASIC Static Timing and Synthesis Engineer for a long-term contract with Northrop Grumman in Baltimore, Maryland. This role involves working on static timing analysis and timing closure for complex digital design projects.

Candidates must possess an active Secret clearance and have significant experience in EDA tools. A strong background in communication and team collaboration is essential. The position may transition to a full-time role for suitable candidates.

Qualifications

• Secret government clearance within the last 5 years.
• 8 years experience (BSEE) or 5 years (MSEE) in static timing & RTL Design.
• Strong oral, written, and interpersonal communication skills.

Responsibilities

• Develop level timing constraints with systems architect/IP experts.
• Collaborate with physical design team on constraints and timing closure.
• Act as hands-on technical contributor.

Skills

Static Timing Analysis

EDA tools knowledge

Team collaboration

Scripting (tcl, csh, perl)

Education

BSEE or MSEE

Tools

Synopsys Primetime-SI

Synopsys Design Compiler

Cadence Encounter Timing system

Linux

Windows

SVN

Git

Job description

ASIC Static Timing and Synthesis Engineers (00005)

Client: Northrop Grumman

Position: ASIC Static Timing and Synthesis Engineers (00005)

Duration: Long term contract (a year+) or CTH (NG will offer FT opportunity after a year for the right candidate, if candidate is interested)

Clearance: Active Secret (No interim or inactive)

Job Description: STA (Static Timing Analysis) Design Engineer - looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies.

Responsibilities

• Work with systems architect/IP experts to develop level timing constraints
• Work with physical design team on design constraint and timing closure
• Be hands‑on technical individual contributor

Requirements

• Secret government clearance within last 5 years
• Good knowledge of EDA tools and scripting
• BSEE with 8 years of experience or MSEE with 5 years’ experience in static timing & RTL Design
• Must be a very good team player with a very good oral, written and interpersonal communication skills

Tool Experience

• Synopsys Primetime‑SI, Synopsys Design Compiler, Cadence Encounter Timing system
• Scripting languages – tcl, csh, perl, Makefile
• Operating systems: linux, windows
• Revision control: SVN, git
• Experience with RTL synthesis
• Experience with ARM CPUs, peripherals such as I2C, SPI, UART, Asynchronous interface designs, peripherals and interconnect protocols such as AHB, AXI, PCIE etc

EEO Statement

All your information will be kept confidential according to EEO guidelines.