ASIC/SOC DFT Engineer (Silicon Engineering)

United States Digital Space LLC; Austin (TX); On-site; USD 90,000 - 130,000; Full time

Job summary

United States Digital Space LLC is seeking an ASIC/DFT Engineer to develop next-gen ASICs for space and ground infrastructure, including scanning and ATPG content. The role involves cross-disciplinary collaboration with systems, firmware, and design teams to ensure high-quality silicon and test coverage.

The candidate should have a background in ASIC design flow and be comfortable working in a dynamic environment with evolving requirements.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience working with ASICs.
• Experience in scan insertion or DFT setup.
• Familiar with Verilog/SystemVerilog, UPF, and DFT/DRC tools.
• Ability to work in a dynamic, cross-disciplinary team.

Responsibilities

• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools.
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems.
• Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage.
• Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals.
• Run and debug non-timing and SDF annotated gate level simulations.
• Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation.
• Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon.

Skills

ASICs

Scan insertion

DFT

Scripting (Python, Perl)

Education

Bachelors in EE/CE/CS

Tools

Verilog/SystemVerilog

UPF

DFT tools

Synthesis tools

Job description

the company was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today the company is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars.

ASIC/SOC DFT ENGINEER (SILICON ENGINEERING)

At the company we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
• Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
• Run and debug non-timing and SDF annotated gate level simulations
• Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
• Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 1+ years of professional experience working with ASICs
• Experience in scan insertion or DFT setup

PREFERRED SKILLS AND EXPERIENCE:

• Understanding of ASIC design flow, methodologies, physical design, and verification
• Experience with high reliability design and implementations
• Good scripting skills (csh/bash, Perl, Python etc.)
• Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
• Familiar with UPF (unified power format), formal verification, and DRC rule checking experience
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s Aff… applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].