Principal DFT Engineer (Silicon Engineering)

United States Digital Space LLC; Austin (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

United States Digital Space LLC is seeking a Principal DFT Engineer to lead the design and optimization of DFT architectures for space‑grade ASICs used in Starlink deployment. You will collaborate with cross‑disciplinary teams to develop test strategies, implement ATPG patterns, and ensure design readiness through RTL and hardware validation.

The role requires 10+ years in ASICs with DFT, scan insertion, and formal verification, plus experience with Verilog/SystemVerilog.

Qualifications

• Bachelor’s degree in electrical or computer engineering or computer science.
• 10+ years of experience with ASICs and DFT setup, integration and validation.
• Strong background in scan insertion, ATPG patterns, and pattern compression.

Responsibilities

• Lead implementation and optimization of DFT architectures using RTL and gate netlists.
• Own ATPG tools and pattern generation for stuck‑at, transition, and path delay faults.
• Evaluate design readiness for scan insertion via RTL and physical design DRC tools.
• Integrate and verify DFT fabrics and IP within Subsystems.
• Run non‑timing and SDF‑annotated simulations; debug issues.
• Develop test scripts and automate processes with Python, Perl, Tcl, or C+.

Skills

DFT architectures

ASIC design

RTL debugging

Verilog/SystemVerilog

Python/Perl scripting

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Tools

Siemens Tessent

UPF

DRC/Scan tooling

Job description

the company was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today the company is actively developing the technologies to make this possible, with the ultimate goal ofenabling human life on Mars.

PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)

At the company we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
• Own ATPG tools and methodologies, including generating patterns for stuck‑at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post‑silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Run and debug non‑timing and SDF annotated gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 10+ years of experience working with ASICs
• 10+ years of experience in scan insertion and DFT setup, integration and validation

PREFERRED SKILLS AND EXPERIENCE:

• Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
• RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
• Ability to solve complex problems including clock domain crossings and power optimization
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
• Familiar with advanced silicon process and technology nodes for high speed and low power consumption
• Strong implementation or integration of design blocks using Verilog/SystemVerilog
• Experience working with ATE testers and test teams

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as needed to meet critical milestones

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s Affi­? reach [e-mail].