ASIC/RTL Design Engineer

TPI Global Solutions; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

A leading company is seeking a Talent Acquisition Professional specialized in semiconductor and automotive domains. This role involves recruiting candidates with expertise in ASIC design, RTL, and SystemVerilog, along with responsibilities encompassing documentation, collaboration with teams, and ensuring project quality. Candidates with 5-6 years of relevant experience will excel in this mid-senior level position, offering a contract duration of over 12 months.

Qualifications

• 5-6+ years' experience with a proven track record in ASIC design.
• Experience in designing RTL blocks for SOCs and integrating ASIC IP.
• Experience with tools used in verification and physical design.

Responsibilities

• Write micro-architecture documentation for design and implementation.
• Collaborate with teams for requirements and high quality designs.
• Participate in silicon bring-up and automate design processes.

Skills

SystemVerilog

ASIC design

RTL design

synthesis

static timing analysis

scripting

communication

Job description

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Talent Acquisition Professional, Hiring Candidates for Semiconductor & Automotive Domain (DV, PD, RTL, ASIC, FPGA, PCB,Layout,Storage,Firmware,Device…

Location: San Jose, CA

Duration: 12+ Months

Interviews: 2 interviews, virtual or onsite is fine.

• Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc.
• scripting is nice to have

Key Responsibilities:

• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture and hardware teams to understand the requirements.
• Work with verification and physical design teams to achieve high quality design and successful tape out.
• Design and implement logic functions that enable efficient test and debug.
• Participate in silicon bring-up for features owned.
• Contribute in cross-functional teams to solve Client problems across multiple functional areas in development of required features.
• Implement automation to increase design team efficiency.

Required:

• 5-6+ years' experience required
• Must have proven track record of ASIC design on several production tape-outs.
• Experience in Designing RTL block for an SOC.
• Experience in integrating ASIC IP into an SOC.
• Experience with synthesis, static timing analysis & optimizations.

Nice-to-have:

• Experience writing timing constraints and exceptions.
• Experience with automation using scripting techniques such as PERL, Python or Tcl
• Experience in Power-saving techniques.
• Experience with Arm architecture and APB, AXI, CHI protocols.
• Experience with design involving Interconnects.
• Ability to develop clear and concise engineering documentation.
• Ability to organize and present complex technical information.
• Strong verbal and written communication skills

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Job function

  Information Technology

• Industries

  Semiconductor Manufacturing and Manufacturing

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