ASIC Physical Design Engineer

Cisco; Austin (TX); On-site; USD 150,000 - 240,000; Full time

Job summary

Cisco is seeking a Physical Design Engineer in Austin to lead RTL-to-GDSII work for sub-16nm to 2nm nodes. You will drive floorplanning, place-and-route, clock/power distribution, and timing convergence across teams to deliver high-performance networking chips.

The role requires hands-on ASIC design experience, emphasis on floorplanning and STA, and collaboration with RTL, DFT, and EDA partners. Cisco provides a comprehensive benefits package and a path for technical growth.

Qualifications

• Minimum: Bachelors in Electrical Engineering with 5+ years of related experience OR Masters with 2+ years OR PhD with 0+ years.
• Hands-on experience in ASIC physical design and implementation.
• Experience with hierarchical floorplanning, clock/power distribution, global signal and I/O planning, physical convergence, timing closure.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define and execute hierarchical floor planning, place-and-route, clock and power distribution, and timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps; recommend tool/flow/methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design efficiency.

Skills

ASIC physical design

Floorplanning

Timing closure

Power integrity

High-gate designs

Education

Bachelors in Electrical Engineering

Masters in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys FC

PrimeTime

Mentor Calibre

Genus

Job description

The application window is expected to close on: 10/08/2026

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products. We design networking hardware for enterprises, service providers, the public sector, and nonprofit organizations worldwide. As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry.

Your Impact

Role

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Minimum Qualifications

• Bachelors degree in Electrical Engineering+ 5 years of related experience, or Masters degree in Electrical Engineering+ 2 years of related experience, or PhD in Electrical Engineering 0+ years of related experience.
• Hands-on experience in ASIC physical design and implementation.
• Experience working with hierarchical floorplanning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology.
• Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm).

Preferred Qualifications

• Experience with Scripting using languages such as TCL, Python and efficient use of AI tools.
• Place & Route experience using tools such as Cadence Innovus or Synopsys FC.
• Synthesis experience including Cadence Genus/Synopsys FC.
• Formal Verification experience using tools such Synopsys Formality or Cadence LEC
• Experience with Static Timing Analysis including tools such as PrimeTime-DMSA.
• Experience with Power Integrity including tools such as Apache Redhawk/Voltus
• Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees On Sales Plans Earn Performance-based Incentive Pay On Top Of Their Base Salary, Which Is Split Between Quota And Non-quota Components, Subject To The Applicable Cisco Plan. For Quota-based Incentive Pay, Cisco Typically Pays As Follows

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area

$167,700.00 - $282,000.00

Non-Metro New York State & Washington State

$149,100.00 - $250,900.00

• For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
• Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.