ASIC Design Hardware Engineer - SDC/STA (Hybrid)

Cisco; San Jose (CA); On-site; USD 155,000 - 223,000; Full time

Benefits offered by this job

Onsite gym

Healthcare

Cafe

Social interest groups

Philanthropy

Job summary

Cisco's Silicon One team in San Jose is seeking a diligent Design/SDC Engineer to own timing constraints from block to full-chip, collaborating with Front-end and Back-end teams to enable physical design closure.

You will implement clocks, SDCs, and scripts using TCL, Synopsys Primetime, TimeVision, and related tools; opportunities to RTL design or IP integration.

Qualifications

• Bachelor’s Degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience or Master’s Degree with 2+ years of ASIC or related experience.
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), STA tools such as Primetime and must have knowledge of HDL such as Verilog/SystemVerilog programming, and scripting languages such as Shell, Perl, and TCL.
• Experience with digital design concepts (eg. clocking, timing exceptions and async boundaries).
• Experience with block/full chip SDC development in functional and test modes.
• Experience with microarchitecture and RTL implementation.

Responsibilities

• Being a member of design team who develops block level and full-chip SDCs and works with physical design and DFT teams to close full-chip timing in multiple timing modes.
• You will work design and architecture teams in understanding clocking structure, develop timing constraints and validate them though constraints verification tool before releasing them for physical design.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to full-chip, and to push down full-chip SDCs to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and collaborate with RTL design owners on SDC development.
• Contribute to full-chip clocking design including diagrams and related documentation.

Skills

Timing constraints

SDC/STA tooling

Verilog/SystemVerilog

Scripting TCL

Clocking concepts

Education

Bachelor's in Electrical or Computer Engineering

Master's in Electrical or Computer Engineering

Tools

Synopsys DC/DCG/FC

Primetime

TimeVision

TimeVision (TCM)

Job description

The application window is expected to close on: 09/24/2026

This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 4-5 days per week.

Meet the Team

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also have an opportunity to work with other ASIC teams in the journey of taking it from concept to first customer shipments.

Your Impact

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and full-chip and validate them using industry standard timing constraints verification tools such as TCM, Timevision. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

• Being a member of design team who develops block level and full-chip SDCs and works with physical design and DFT teams to close full-chip timing in multiple timing modes.
• You will work design and architecture teams in understanding clocking structure, develop timing constraints and validate them though constraints verification tool before releasing them for physical design.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to full-chip, and to push down full-chip SDCs to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and collaborate with RTL design owners on SDC development.
• Contribute to full-chip clocking design including diagrams and related documentation.

Minimum Qualifications

• Bachelor’s Degree in Electrical or Computer Engineering with 4+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 2+ years of ASIC or related experience.
• Experience with synthesis tools (eg. Synopsys DC/DCG/FC), STA tools such as Primetime and must have knowledge of HDL such as Verilog/SystemVerilog programming, and scripting languages such as Shell, Perl, and must have strong experience scripting with TCL.
• Experience with digital design concepts (eg. clocking, timing exceptions and async boundaries).
• Experience with block/full chip SDC development in functional and test modes.
• Experience with microarchitecture and RTL implementation.

Preferred Qualifications

• Effective documentation, problem-solving, and technical communication skills.
• Experience working cross-functionally and collaborating with various technical teams.
• You are a problem solver who loves to tackle new challenges and a self-starter who is highly motivated and thrives on innovative technology.
• You are a strong communicator in a team setting, enjoy working in a dynamic team environment, and are an out-of-the-box thinker.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada:

The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees On Sales Plans Earn Performance-based Incentive Pay On Top Of Their Base Salary, Which Is Split Between Quota And Non-quota Components, Subject To The Applicable Cisco Plan. For Quota-based Incentive Pay, Cisco Typically Pays As Follows

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area

$155,000.00 - $256,000.00

Non-Metro New York State & Washington State

$138,100.00 - $227,900.00

• For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
• Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.