ASIC Methodology Engineer: Design Analytics Platform

Qualcomm; Santa Clara (CA); On-site; USD 153,200 - 229,800; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego or Santa Clara, CA, seeks a member of the DTECH Methodology team to enable a state‑of‑the‑art design analytics platform and drive improvements in power, performance, and area.

You will collaborate with core and SOC teams, applying STA tools such as PrimeTime and Tempus, and contribute to ASIC/VLSI flows to optimize design quality and reliability.

Qualifications

• MS/PhD in Electrical Engineering or Computer Science with 1–2 years of ASIC/VLSI tool experience.
• Strong Python programming skills.
• Hands-on experience with static timing analysis (STA) tools, e.g. PrimeTime and Tempus.
• Problem-solving and analytical mindset.
• Bachelor's degree and 4+ years in ASIC design/verification.
• Master's degree and 3+ years in ASIC design/verification.
• PhD and 2+ years in related work.

Responsibilities

• Enable a state-of-the-art design analytics platform within the DTECH team.
• Collaborate with core and SOC groups to improve power, performance, and area.
• Contribute to tool flows and enable scalable design analysis.

Skills

Python programming

Analytical mindset

Problem solving

Education

MS/PhD in Electrical Engineering or Computer Science

Bachelor's degree in Science or Engineering

Tools

PrimeTime

Tempus

Perforce

Git

Job description

Qualcomm Technologies, Inc. in San Diego or Santa Clara, CA, seeks a member of the DTECH Methodology team to enable a state‑of‑the‑art design analytics platform and drive improvements in power, performance, and area.

You will collaborate with core and SOC teams, applying STA tools such as PrimeTime and Tempus, and contribute to ASIC/VLSI flows to optimize design quality and reliability.