ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA) (North Reading, MA, US)

LitePoint; North Reading (MA); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Discretionary bonus

Health benefits

Job summary

Teradyne, a global test and automation leader, is seeking an ASIC/FPGA Methodology Engineer to define and maintain FPGA/ASIC design workflows in a Linux environment.

You will collaborate with design and verification teams, optimize flows with Vivado/Quartus, and implement CI/CD pipelines using Jenkins, Docker, and Git.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 3+ years of FPGA and embedded design experience.
• Proficiency with Verilog/SystemVerilog and UVM.
• Experience with FPGA tools Vivado and Quartus.
• Familiarity with ASIC design flows and methodologies.
• Experience with Git, Docker, LSF, Jenkins and CI/CD workflows.

Responsibilities

• Develop and maintain ASIC/FPGA design, verification, and implementation methodologies.
• Collaborate with design and verification teams to integrate workflows and tools.
• Support RTL design using Verilog and debug hardware issues.
• Optimize FPGA tool flows (Vivado, Quartus).
• Implement CI/CD pipelines with Jenkins, Docker, Git.
• Utilize Linux tools to support workflows.
• Provide guidance on FPGA/ASIC methodologies.
• Stay current with industry trends to improve design methods.

Skills

FPGA design

Embedded design

SystemVerilog/UVM

CI/CD workflows

Linux tooling

Education

Electrical/Computer Eng

Tools

Vivado

Quartus

Git

Docker

LSF

Jenkins

Artifactory

ClearCase

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

The ASIC/FPGA Methodology Engineer will play a critical role in defining, developing, and maintaining methodologies and workflows for FPGA and ASIC design and verification. The ideal candidate will have a strong foundation in FPGA and embedded design, coupled with expertise in modern development tools in a Linux-based environment. This role requires a proactive individual who thrives in a collaborative environment and is passionate about driving innovation in hardware design.

Key Responsibilities

• Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation.
• Collaborate with design and verification teams to ensure seamless integration of workflows and tools.
• Support the development of RTL designs using Verilog and assist in debugging complex hardware issues.
• Optimize design flows for FPGA tools such as Vivado, Quartus, or similar platforms.
• Implement and manage CI/CD pipelines using tools like Jenkins, Docker, and Git to streamline development processes.
• Utilize Linux utilities (e.g., Git, Docker, LSF, Clearcase) to support design and verification workflows.
• Provide technical guidance and training to team members on best practices for FPGA/ASIC methodologies.
• Stay updated on industry trends and emerging technologies to continuously improve design methodologies.

All About You

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of industry experience in FPGA and embedded design.
• Strong understanding of FPGA and embedded design principles.
• Hands-on experience with FPGA development tools (e.g., Vivado, Quartus).
• Familiarity with ASIC design flows and methodologies.
• Proficiency in utilities such as Git, Docker, LSF, Jenkins, Artifactory, and Clearcase.
• Knowledge of CI/CD workflows and automation tools.
• Understanding of digital design verification methodologies (e.g., SystemVerilog, UVM).
• Experience with timing analysis, synthesis, and timing closure for FPGA/ASIC designs.
• Familiarity with system-level integration and validation.
• Strong problem-solving skills and the ability to debug complex hardware/software issues.

Compensation

The base salary range for this role is $154,900-$247,800. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.