ASIC and Logic Design Engineering Manager (Compute Test, North Reading) (North Reading, MA, US)

LitePoint; North Reading (MA); On-site; USD 156,000 - 249,000; Full time

Benefits offered by this job

Health benefits

Dental

Vision

Retirement plan

Paid vacation

Tuition assistance

Job summary

Teradyne is seeking a Logic Design Manager to lead a 4–6 person FPGA/ASIC team in designing and verifying FPGA/SoC blocks for Compute Test products. You will collaborate with mixed-signal ASIC, PCB, software and systems teams to meet product requirements and schedules.

The role requires hands-on FPGA/ASIC experience, leadership capability, and strong RTL experience with Cadence, Vivado/Quartus, and verification methods. Manage budgets, staffing, and remote resources in a fast-paced environment.

Qualifications

• BSEE or MSEE and 12+ years of experience in Digital FPGA design; digital ASIC experience a plus.
• At least 5 years as FPGA/ASIC project lead driving multiple projects end-to-end.
• Proficient in RTL coding (Verilog preferred) and digital simulation tools.
• Experience with PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES.
• Familiar with AMD or Altera FPGAs and development tools (Vivado/Quartus).
• Experience with LINT, CDC, and bug tracking tools (Jira, etc.).
• Experience with source control and CI; familiarity with UVM is a plus.
• Strong presentation and communication skills; team leadership and scheduling capabilities.

Responsibilities

• Lead multiple FPGA/digital IP development projects (2–3 concurrently).
• Oversee staffing, budgets, and remote resources as needed.
• Represent the FPGA team on core project teams and reviews.
• Contribute to FPGA implementation and provide HW sustaining support.
• Coach and manage a 4–6 person team; drive process improvements.
• Collaborate across engineering disciplines to meet product requirements.

Skills

RTL coding

Verilog

Digital FPGA design

Digital ASIC design

Project leadership

FPGA/ASIC RTL verification

Cadence tools

Vivado

Quartus

UVM

Static timing analysis

Jira

Git

Source control

Microsoft Project

C/C++

Embedded processors

Education

BSEE or MSEE

Tools

Cadence

Vivado

Quartus

Git

Clearcase

CVS

UVM

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGA’s for Teradyne Compute Test Division’s next generation products. In this role you will lead a team of ~4-6 engineers in a fast-paced environment to help the organization meet key business needs. Requires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products. You should have hands-on experience with complex FPGA (and preferably digital ASIC) SOC designs for real-world products. You also should have a proven track record of managing engineering teams toward timely deliverables and successful project completion.

• Lead multiple simultaneous (typically 2-3) FPGA or digital IP development projects.
• Typically includes oversight of some remote resources.
• Planning and tracking of project schedule and budget.
• Manage project staffing levels including both full time and contract resources.
• Represent the FPGA team on project core teams and at program reviews.
• Contribute to FPGA implementation (i.e. code RTL blocks) as needed.
• Provide technical support for HW sustaining issues.
• Set goals, provide coaching and manage compensation of a 4-6 person team.
• Contribute to FPGA team process improvement initiatives.
• Collaborate with other engineering and business disciplines to ensure that FPGA and IP deliverables satisfy all product requirements.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEE or MSEE and 12+ years of relevant experience in Digital FPGA design and integration (Digital ASIC experience is a plus).
• Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release.
• Extensive experience coding RTL (verilog preferred).
• Extensive experience using digital simulation tools (Cadence preferred).
• Extensive experience using static timing analysis tools.
• Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES
• Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both.
• Experience using digital design quality tools e.g. LINT, CDC.
• Experience with bug tracking tools (Jira etc.)
• Experience with source control systems (Clearcase, Git, CVS) and continuous integration.
• Familiarity with digital verification tools and methodologies (preferably UVM).
• Experience with project scheduling tools (e.g. Microsoft project)
• Experience with embedded processors and digital signal processing is a plus.
• Experience with high level programming languages (C, C++) is a plus.
• Excellent presentation and communication skills.
• Preferred: Experience developing hardware for automated test equipment is a plus.
• Preferred: 2-3 years of experience as a first level manager of an engineering team.

Compensation

The base salary range for this role is $155,500 - $ 248,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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