ASIC Engineer, Design

Meta; Jackson (MS); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Responsibilities include architecture exploration, micro-architecture development, IP integration and collaboration with verification and emulation teams on test plans, plus coordination with the implementation team to close design on timing and power. Strong RTL skills (Verilog/SystemVerilog) are required.

Qualifications

• Bachelor's degree or equivalent practical experience in a technical field
• 8+ years in micro-architecture/RTL development or SoC micro-architecture design and integration
• RTL development using Verilog, SystemVerilog and HLS

Responsibilities

• Architecture exploration across block IPs and subsystems
• Develop micro-architecture for complex control and data path IPs
• Identify, select and integrate soft and hard IP, collaborate with verification and emulation to develop test plans
• Work with implementation teams to meet timing and power goals

Skills

Architecture exploration

Micro-architecture development

IP integration

Test plan collaboration

Timing & power optimization

RTL design

Verilog/SystemVerilog

Education

Bachelor's degree in Computer Science/Engineering or related field

8+ years in micro-architecture/RTL or SoC micro-architecture

RTL development using Verilog/SystemVerilog/HLS

Tools

Synthesis

Timing Closure

Formal Verification

Job description

Summary:

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

Required Skills:

ASIC Engineer, Design Responsibilities:

1. Architecture exploration
2. Micro-architecture development
3. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
4. Collaboration with implementation team to close the design on timing and power

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
2. 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
3. RTL development using Verilog, System Verilog and HLS

Preferred Qualifications:

Preferred Qualifications:

1. Experience in CPU, NOC, Memory and Peripheral Subsystems
2. Experience with Synthesis, Timing Closure and Formal Verification Methodology
3. Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
4. Experience in data path development

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affi­rmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].