ASIC Efficiency Engineer: Boost PPA, GPUs & Equity

NVIDIA; Santa Clara (CA); On-site; USD 116,000 - 189,750; Full time

Job summary

NVIDIA seeks an ASIC Design Efficiency Engineer to innovate HW/RTL for next-generation GPUs and processors across mobile, embedded, and data center platforms. You will contribute to design targets, performance, and power-efficiency enhancements while collaborating with architects and VLSI teams.

The role requires a strong background in HDL, logic design, and system architecture, with a focus on efficient, scalable design methodologies and cross-disciplinary teamwork.

Qualifications

• Proficiency in SystemVerilog or similar HDL.
• Solid understanding of logic design and computer architecture.
• Strong interpersonal skills and ability to work in a diverse product-oriented team.

Responsibilities

• Develop innovative HW, GPU, and system designs to extend performance and efficiency.
• Understand the design and implementation, develop methodology and infrastructure to drive PPA improvements.
• Execute and deliver fully verified, high performance RTL to achieve design targets.
• Collaborate with architects, designers, verification and VLSI teams to craft top performing GPUs.

Skills

SystemVerilog proficiency

Logic design

Interpersonal skills

ASIC/RTL experience

Education

Bachelor's degree in EE/CE

Job description

NVIDIA seeks an ASIC Design Efficiency Engineer to innovate HW/RTL for next-generation GPUs and processors across mobile, embedded, and data center platforms. You will contribute to design targets, performance, and power-efficiency enhancements while collaborating with architects and VLSI teams.

The role requires a strong background in HDL, logic design, and system architecture, with a focus on efficient, scalable design methodologies and cross-disciplinary teamwork.