ASIC Design Efficiency Engineer

NVIDIA; Santa Clara (CA); On-site; USD 116,000 - 189,750; Full time

Job summary

NVIDIA seeks an ASIC Design Efficiency Engineer to innovate HW/RTL for next-generation GPUs and processors across mobile, embedded, and data center platforms. You will contribute to design targets, performance, and power-efficiency enhancements while collaborating with architects and VLSI teams.

The role requires a strong background in HDL, logic design, and system architecture, with a focus on efficient, scalable design methodologies and cross-disciplinary teamwork.

Qualifications

• Proficiency in SystemVerilog or similar HDL.
• Solid understanding of logic design and computer architecture.
• Strong interpersonal skills and ability to work in a diverse product-oriented team.

Responsibilities

• Develop innovative HW, GPU, and system designs to extend performance and efficiency.
• Understand the design and implementation, develop methodology and infrastructure to drive PPA improvements.
• Execute and deliver fully verified, high performance RTL to achieve design targets.
• Collaborate with architects, designers, verification and VLSI teams to craft top performing GPUs.

Skills

SystemVerilog proficiency

Logic design

Interpersonal skills

ASIC/RTL experience

Education

Bachelor's degree in EE/CE

Job description

We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!

What You'll Be Doing

• Develop innovative HW, GPU, and system designs to extend the state of the art performance and efficiency.
• Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
• Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
• Collaborate with architects, designers, verification and VLSI teams to craft the industry's top performing GPUs.

What We Need To See

• Bachelors Degree in EE or CE or equivalent experience.
• 2+ years of experience.
• Proficiency in SystemVerilog or similar HDL.
• Solid understanding of logic design and computer architecture.
• Strong interpersonal skills and ability to work in a diverse product-oriented team.

Ways To Stand Out From The Crowd

• Pipeline processor or deep learning accelerator design/architecture experience.
• Performance verification, low power or physical (synthesis/VLSI) design experience.
• Scripting knowledge in Python/Perl.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until July 14, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.