ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior)

Boeing; Mountain View (CA); On-site; USD 120,000 - 240,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

Boeing Defense, Space and Security is hiring ASIC Design Engineers in Mountain View, CA, to contribute to DFT and Physical Design for space/aerospace ASICs. You will work on TAP/JTAG/IJTAG, MBIST, and timing closure for complex digital subsystems.

Role spans design, verification, and tapeout readiness with cross‑discipline collaboration and mentoring responsibilities. Onsite work is required at Mountain View, CA.

Qualifications

• US citizenship and ability to obtain a US security clearance.
• Bachelor of Science in Engineering or related field.
• 5+ years of ASIC/FPGA design for test or physical design.
• Proficiency in scripting (Tcl, Python, Perl).

Responsibilities

• Design and implement DFT architectures and test access mechanisms: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, memory BIST, and scan compression.
• Develop and validate TAP/JTAG and IJTAG infrastructures; produce BSDL/ICL/PDL artifacts; support ATPG pattern generation and coverage optimization.
• Drive pattern generation, memory test validation, at‑speed test, silicon debug (scan, at‑speed, bring‑up), and post‑silicon validation.
• Perform synthesis, equivalence checking, static timing analysis (STA), constraints generation/management, timing convergence and ECO implementation at block and chip level.
• Support clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, backend partners, and vendors.
• Support chip‑level integration, top‑level timing closure, signoff readiness, and tapeout activities.
• Contribute to methodology development, automation, tool evaluations, flow documentation, and deployment of best practices for next‑generation products.
• Troubleshoot complex cross‑domain timing and CDC issues; propose and implement robust, repeatable fixes.
• Coordinate with external partners/customers on custom DFT interfaces, security, and backend flows as applicable.
• Mentor engineers and lead technical efforts (for senior/lead levels).
• Occasional travel and after‑hours meetings during critical milestones.

Skills

ASIC/FPGA design

DFT

Synthesis

STA

TAP/JTAG

IJTAG

Python scripting

Debug

Education

Bachelor's degree in Engineering

Tools

TAP/JTAG tooling

MBIST

BSDL/ICL/PDL

EDA tools

Job description

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us.

Boeing Defense, Space and Security is hiring ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) at various levels of experience to join the team in Mountain View, CA.

Boeing Space, Intelligence & Weapons Systems organization is seeking multiple ASIC engineers across experience levels to advance mission‑critical digital subsystems. Candidates may focus on Design‑for‑Test (DFT) / ASIC backend test infrastructure, or on Physical Design (synthesis and static timing analysis) responsibilities. You will work on leading‑edge ASICs used in space and aerospace systems—driving architecture, verification, tapeout readiness, silicon debug, and cross‑discipline integration with architecture, RTL, verification, DFT, and external backend partners.

Position Responsibilities

• Design and implement DFT architectures and test access mechanisms: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, memory BIST, and scan compression.
• Develop and validate TAP/JTAG and IJTAG infrastructures; produce BSDL/ICL/PDL artifacts; support ATPG pattern generation and coverage optimization.
• Drive pattern generation, memory test validation, at‑speed test, silicon debug (scan, at‑speed, bring‑up), and post‑silicon validation.
• Perform synthesis, equivalence checking, static timing analysis (STA), constraints generation/management, timing convergence and ECO implementation at block and chip level.
• Support clean netlist handoffs and predictable convergence by partnering with RTL, verification, DFT, backend partners, and vendors.
• Support chip‑level integration, top‑level timing closure, signoff readiness, and tapeout activities.
• Contribute to methodology development, automation, tool evaluations, flow documentation, and deployment of best practices for next‑generation products.
• Troubleshoot complex cross‑domain timing and CDC issues; propose and implement robust, repeatable fixes.
• Coordinate with external partners/customers on custom DFT interfaces, security, and backend flows as applicable.
• Mentor engineers and lead technical efforts (for senior/lead levels).
• Occasional travel and after‑hours meetings during critical milestones.

This position is expected to be 100% onsite. The selected candidate will be required to work onsite at the listed location.

Basic Qualifications (Required Skills/Experience)

• This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final US Secret Clearance Post-Start is required.
• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
• 5+ years of ASIC/FPGA design for test or physical design experience
• Proficiency in scripting for automation and analysis (Tcl, Python, Perl).

Preferred Qualifications (Desired Skills/Experience)

• Lead, Level 4: 9+ years related engineering experience and demonstrated technical leadership.
• Senior, Level 5: 14+ years related engineering experience and demonstrated technical leadership.
• Strong analytical, problem‑solving, and communication skills
• Bachelor’s or Master’s Degree in EE, Computer Engineering/Science, or related field.
• For DFT roles: Hands‑on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at‑speed test, and silicon debug. Familiarity with BSDL/ICL/PDL artifacts.
• For Physical Design roles: Practical experience in synthesis and static timing analysis (STA), constraints generation/management, logic synthesis, equivalence checking, and ECO flows.
• Active US Secret Clearance.
• Experience with large, timing‑challenging ASIC blocks, cross‑domain timing convergence, and full physical design flow (synthesis, floorplanning, place & route, CTS, STA, physical verification).
• Background in radiation‑hardened or space‑qualified ASIC design.
• FPGA implementation experience including constraints and timing closure.
• Understanding of timing fundamentals and CDC concepts.
• Familiarity with UPF/CPF power intent, power closure flows, and DFT interplay with power domains.
• Requirements development and traceability experience.
• Experience working with external backend partners, multi‑disciplinary teams, and vendors.
• Familiarity with industry‑standard EDA tools and DFT/physical design methodologies.
• Mentoring, team leadership, or formal technical lead experience.

Conflict of Interest

Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.

Typical Education/Experience

Experienced, Level 3

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Lead, Level 4

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Senior, Level 5

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

Relocation

This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.

Drug Free Workplace

Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.

Shift Work

This position is for 1st shift.

Total Rewards

At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications, as well as market and business considerations.

Summary pay range for Experienced, (Level 3): $119,850 - $162,150

Summary pay range for Lead, (Level 4): $146,200 - $197,800

Summary pay range for Senior, (Level 5): $176,800 - $239,200

Applications for this position will be accepted until Oct. 17, 2026

Export Control Requirements

• 120.62 is required. “U.S. Person” includes U.S. Citizen, U.S. National, lawful permanent resident, refugee, or asylee.

Export Control Details

US based job, US Person required

Education

Bachelor's Degree or Equivalent Required

Security Clearance

This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship. An interim and/or final US Secret Clearance Post-Start is required.

Visa Sponsorship

Employer will not sponsor applicants for employment visa status.

Shift

This position is for 1st shift

Equal Opportunity Employer

Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.