ASIC Design Engineer — IP Integration & Implementation

Apple Inc.; Sunnyvale, Northern (CA, KY); Hybrid; USD 150,000 - 278,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock plans

Tuition reimbursement

Relocation assistance

Job summary

Apple is seeking an ASIC Design Engineer in the Pixel IP design team to deliver high-performance, low-power pixel processing engines for next-generation SoCs.

In this front-end role you will write micro-architectural specs and RTL, collaborate with architecture, design and verification teams, and optimize timing, area and power with physical design.

Apple also provides comprehensive benefits, stock plans, tuition reimbursement and relocation support.

Qualifications

• Bachelor’s degree and 3+ years of relevant industry experience.
• Prefer IP/SoC design experience and chip/subsystem integration.
• ASIC/FPGA design methodology experience: synthesis, static timing, ESL checks, floorplanning and timing closure.
• System design with multiple clock and reset domains.
• Familiarity with AMBA protocols (AXI, AHB, APB).
• Experience with low-power design, UPF, and scripting (Python/Perl/TCL).
• Strong collaboration and communication skills.

Responsibilities

• Write detailed micro-architectural and integration specifications.
• Design digital hardware by writing RTL with embedded assertions and cover points.
• Work with physical design teams to optimize timing, area and power.
• Ensure designs follow best practices for power, clock and reset domains.
• Collaborate with verification and formal verification teams to debug and verify functionality and performance.

Skills

ASIC/SoC design

RTL coding

Digital hardware design

Power optimization

Verif/Formal verification

Collaboration

Front-end design

Education

Bachelor's degree, 3+ years of experience

Tools

Python

UPF power intent

AMBA protocols (AXI/AHB/APB)

Job description

Do you love creating elegant solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!In this highly visible role, you will be at the center of the Pixel IP design effort to capture and display beautiful images and video. You will collaborate with all disciplines, making a critical impact getting functional products to millions of customers quickly.

Description

As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex subsystem integration and implementation. You will work closely with architecture, design, and verification teams to build high performance and low power pixel processing engines. You will have responsibilities spanning all aspects of multimedia IP design.

In this front-end design role, your tasks will include:

• Writing detailed micro-architectural and integration specifications.
• Designing digital hardware by writing high-quality RTL, with embedded assertions and cover points.
• Working with physical design teams to optimize timing, area, and power for our designs in silicon.
• Ensuring that our designs follow industry best practices for handling power, clock, and reset domains.
• Working closely with design verification and formal verification teams to debug and verify functionality and performance.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Learn about reasonable accommodations for job applicants

Apple accepts applications to this posting on an ongoing basis.

Minimum Qualifications

• Bachelor’s degree and 3+ years of relevant industry experience

Preferred Qualifications

• Prefer prior experience in IP/SoC design, integration at the chip or subsystem level, and implementation.
• Industry exposure to and knowledge of ASIC/FPGA design methodology, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
• Experience with system design methodologies that contain multiple clock and reset domains.
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
• Prefer experience in low-power design, tools, and methodologies including UPF power intent specification.
• Familiarity with relevant scripting languages (Python, Perl, TCL).
• Strong collaboration skills, with excellent written and verbal communication.