ASIC Design Engineer

Broadcom; Fort Collins (CO); On-site; USD 62,000 - 99,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grant

Medical, dental, vision

Job summary

Broadcom's Custom Silicon Design Team in Fort Collins, CO, is seeking a Design Engineer focused on the physical implementation of high-performance ASICs. You will work across the full RTL-to-GDSII cycle, engaging with senior engineers and cross-functional partners to deliver cutting-edge silicon in 3 nm and smaller nodes operating above 1 GHz.

Responsibilities include floorplanning, placement, CTS, routing, timing closure, and physical verification using Cadence Innovus and other tools.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering.
• Strong background in VLSI/CMOS concepts and digital design.
• Experience with ASIC physical design tools and flows is a plus.

Responsibilities

• Contribute to physical design implementation of large-scale ASICs.
• Support floorplanning, placement, CTS, routing, timing, and DRC/LVS.
• Collaborate with cross-functional teams for design signoff.
• Utilize EDA tools for design, implementation, and verification.
• Contribute to design flow improvements and sub-micron methodology.

Skills

VLSI design

CMOS logic

Analytical skills

Communication skills

Team collaboration

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

Job description

Job Description:

Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This Design Engineering position focuses on the physical implementation of high-performance ASICs, providing hands‑on experience with the latest 3 nm and smaller process nodes operating at speeds exceeding 1 GHz, from concept through production. The role offers exposure to advanced design methodologies and close collaboration with senior engineers across multiple disciplines to deliver industry‑leading silicon solutions.

Key Responsibilities

• Contribute to the physical design implementation of large-scale ASICs (multi-hundred-million gate complexity).
• Support key design activities including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification (DRC/LVS).
• Collaborate with cross‑functional teams on block‑level integration, timing analysis, and design signoff.
• Utilize both commercial and in‑house EDA tools for design, implementation, and verification.
• Contribute to design flow improvements, automation, and deep sub‑micron methodology development.
• Assist in timing analysis, power planning, IR/EM checks, and post‑route optimization.
• Gain exposure to the complete ASIC design cycle — from RTL to GDSII and silicon bring‑up.
• Interface with customers and internal stakeholders to support technical discussions and design reviews.

Technical Skills / Background

• Solid understanding of VLSI design, CMOS logic, and digital circuit fundamentals.
• Familiarity with ASIC physical design concepts such as placement, routing, and timing.
• Strong analytical and debugging skills, with the ability to quickly learn new tools and flows.

Coding and Tool Proficiency

• Proficiency in UNIX/Linux environments.
• Working knowledge of TCL; familiarity with Python or Perl preferred.
• Exposure to EDA tools such as Cadence Innovus, Synopsys ICC2, or PrimeTime is a plus.

Soft Skills

• Excellent communication, collaboration, and problem‑solving abilities.
• Ability to work effectively with cross‑functional and global teams.
• Highly motivated, detail‑oriented, and eager to learn in a fast‑paced R&D environment.
• Demonstrates strong engineering judgment, ownership, and accountability.

Education and Experience

• Bachelor’s degree in Electrical or Computer Engineering, or
• Master’s degree in Electrical or Computer Engineering.

Compensation and Benefits

The annual base salary range for this position is USD 61,900.00 To USD 99,000.00

As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.