Analog Mixed-Signal Design Engineer

ovt; Santa Clara (CA); On-site; USD 157,000 - 160,000; Full time

Job summary

ovt in California seeks an Analog Mixed-Signal Design Engineer to design, characterize embedded analog circuits including high-speed I/O, SerDes, PLLs, and clocking networks.

You will debug RTL-level signal synchronization, evaluate performance across process variation and temperature, and collaborate with system and test engineers on image sensor interfaces. Proficiency with Cadence tools and HSPICE/Spectre is required.

Qualifications

• Master's degree in Electrical Engineering or related field.
• One year of experience as an Analog Design Engineer.

Responsibilities

• Design, develop, and characterize embedded analog circuits (high-speed I/O, SerDes, FIFO, CDR, PLL).
• Debug RTL level signal synchronization, clock tree, and cross-domain clocks.
• Evaluate performance across process variation, temperature, and noise.
• Analyze layout parasitics and signal integrity using post-layout simulations.
• Collaborate with system/test engineers on image sensor interfaces and clocking.
• Perform layout support, optimization, and Cadence-based simulations.
• Transistor-level IC design and simulation for clock distribution, serializer circuits, and bias/reference circuits.

Skills

Python

C Shell

Scilab

RTL verification

Education

Master's degree in Electrical Engineering

Tools

Cadence Virtuoso

Cadence Simvision

Cadence Layout

HSPICE

Spectre

EZWave

Cadence Viva

EDA scripting

Job description

Job Title: Analog Mixed-Signal Design Engineer

Job Duties:

• Design, develop, and characterize embedded analog circuits, such as high speed I/O, SerDes, FIFO, CDR, PLL, etc.
• Design and debug RTL level signal synchronization, clock tree and conduct cross domain clock designs.
• Evaluate and characterize the circuit performance under various conditions such as process variation and mismatches, power supply change, high/low working temperature, noise and crosstalk.
• Perform analysis of circuits’ performance degradation and signal integrity drop due to layout induced parasitic effects based on simulations with extracted post-layout circuit netlist.
• Work closely with system and test engineers to develop high speed interface, package/board, and system clocks in image sensor and bridge chip products.
• Conduct Layout design and support. Get involved into layout optimizations for high speed or high precision performance directly. Use Cadence analog design/layout flow and spice/spectre MDL simulations.
• Perform transistor level integrated circuit design and simulation. Develop clock generator and distribution tree circuits with low jitter and low duty-cycle distortion. Perform transistor level design of serializer circuit which works up to Gbps data rate within process and temperature corners. Design accurate analog biasing and reference circuit for IO links. Characterize the IO links circuit performance under non-ideal environment (high power supply noise, crosstalk, process variation and mismatches). Use software: Cadence Virtuoso, Cadence Spectre simulator and AFS simulators.
• Cooperate with other circuit designer to solve problems and issues discovered on system level. Assist top-level circuit designer in checking register settings, power and ground layout routing and connections between blocks of the certain circuit.
• Debug and design change solutions on signal integrity, EMI/RFI., ESD/latch up issues. Develop the floor-plan of IO link that is friendly to signal-integrity. Develop and improve ESD circuit on the IC chip to pass industry ESD standards.
• Perform necessary data analysis on simulation results. Write design documents to record design review, updated information, knowledge and lesson learned from projects.

Requirements:

Master’s degree or foreign equivalent degree in Electrical Engineering, Electronic Circuits & Systems, or a related field.

Require one year of experience as an Analog Design Engineer.

• Experience in researching and developing with embedded MIPI C/D-PHY transmitter circuit.
• Expertise in programming using Python, perl, scilab and Cshell;
• Experience with EDA tools such as Cadence Virtuoso, Cadence Simvision, Cadence Layout in circuit design;
• Experience in RTL level functional block behavioral verification;
• Experience in using Hspice, Spectre to build-up analog circuit test bench to perform transistor level simulation on analog/mixed-signal circuits.
• Experience in using EDA tools such as EZwave, Cadence Viva to check the simulation result, plot eye-diagram and evaluate circuit performance.
• Experience with chip test instruments such as oscilloscope, function generator, power supply and network analyzer;
• Experienced with high-speed circuit layout support.

Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.