Analog Layout Engineer

Apple; Waltham (MA); On-site; USD 120,000 - 160,000; Full time

Job summary

Join a forward-thinking company as an Analog Layout Engineer, where your expertise in analog and mixed-signal design will shape the future of cutting-edge systems-on-chip. Collaborate with talented circuit designers to transform innovative ideas into silicon, ensuring optimal performance in advanced technologies. This dynamic role promises continuous learning and collaboration, allowing you to work on complex layouts and contribute to groundbreaking projects that power the next generation of devices. If you are passionate about technology and eager to make a significant impact, this opportunity is perfect for you.

Qualifications

• 10+ years in analog/mixed-signal layout design of deep submicron CMOS circuits.
• Experience with layout designs focusing on matching, low noise, and low power.

Responsibilities

• Deliver fully-verified Analog Mixed-Signal IP within an SOC flow.
• Develop layouts for mixed signal and analog circuits in CMOS technologies.

Skills

Analog Layout Design

Mixed-Signal Layout

CMOS Technologies

FinFET Technologies

Scripting (SKILL, Perl, TCL, Shell, Python)

Communication Skills

Education

B.S. degree

Tools

Cadence Virtuoso

Cadence Innovus

Job description

Analog Layout Engineer

Location: Waltham, Massachusetts, United States

Department: Hardware

Summary

Apple Silicon Engineering Group (SEG) is seeking Analog Layout Engineers to work on the next generation of Apple's systems-on-chip (SOCs). These SOCs, with multi-billion transistors, serve as the core of iPhones and iPads. The focus is on Analog/Mixed-Signal (AMS) circuits, including SerDes for data communication, PLLs for clock generation, and sensors for measuring physical quantities.

As an Analog Layout Engineer, you will transform design ideas into silicon, collaborating with circuit designers and utilizing advanced tools and methodologies. Your work involves crafting custom analog designs to optimize product performance. This role offers continuous learning and collaboration in a dynamic environment.

Responsibilities

1. Deliver fully-verified Analog Mixed-Signal IP within an SOC flow.
2. Develop sophisticated layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies.
3. Review and analyze floorplans and complex circuits.
4. Utilize design verification tools to ensure layout accuracy.
5. Coordinate with circuit design engineers on work planning and layout tradeoffs.
6. Interpret LVS, DRC, and ERC reports to optimize layout completion.
7. Work closely with the circuit team to exceed specifications and expectations.
8. Apply CAD tools and mask design knowledge to deliver accurate layouts matching performance, area, and power requirements.

Minimum Qualifications

• B.S. degree and at least 10 years of relevant industry experience or equivalent.

Preferred Qualifications

• Over 10 years in analog/mixed-signal layout design of deep submicron CMOS circuits, with at least 3 years in FinFET technologies.
• Experience with analog layout designs focusing on matching, low noise, and low power, including CMOS, BJTs, resistors, capacitors, I/O pads, and ESD.
• Ability to identify failure-prone structures and work proactively with the design team.
• Proficiency in custom and standard cell-based floorplanning and hierarchical layout assembly.
• Understanding of IR drop, RC delay, electromigration, self-heating, and coupling capacitance.
• Experience interpreting physical verification reports (DRC, ERC, LVS).
• Proficiency with Cadence Virtuoso's advanced features (XL, EAD, APR, Constraint Manager).
• Scripting skills in SKILL, Perl, TCL, Shell, or Python.
• Strong communication skills and ability to collaborate across teams.
• Additional skills (plus): Cadence Innovus, CAD automation, PCell creation, familiarity with Machine Learning and AI concepts.
• Focus on Mixed-Signal and RF ICs is a plus.

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