AI Systems Engineer, Hardware Architecture

Meta; United States; Remote; USD 210,000 - 320,000; Full time

Job summary

Meta is seeking a senior hardware systems architect to define architecture strategy for on-device AI in wearables, AR/VR devices. You will shape compute and memory hierarchies, camera/IP pipelines, and SoC interfaces, guiding cross-functional teams toward energy-efficient, scalable solutions.

You will lead multi-year roadmaps, evaluate trade-offs, and build models to forecast performance under real AI workloads.

Qualifications

• 12+ years hardware systems architecture experience in AI, imaging, or HPC.
• Deep knowledge of camera pipelines and end-to-end imaging system design.
• Experience defining AI workloads on SoC or system-level architectures.
• Familiarity with real-time computer vision, depth sensing, or VIO.
• Knowledge of hardware/software co-design for on-device AI and imaging workflows.
• Ability to build performance models and evaluate trade-offs with simulations.

Responsibilities

• Develop multi-generation architecture plans for on-device AI inference and training.
• Evaluate compute, memory, interconnect, and power trade-offs for target workloads.
• Architect camera pipelines, sensor interfaces, ISP, and multi-camera synchronization.
• Set requirements and targets for AI accelerators, image processors, and SoCs.
• Build performance models and simulations to compare designs under real workloads.
• Collaborate with silicon, firmware, camera, and ML teams to boost end-to-end performance and energy efficiency.
• Provide technical direction and communicate architecture decisions to leadership.
• Assess external technologies and suppliers for long-term roadmap planning.

Skills

AI hardware

Imaging systems

SoC design

Memory interconnect

Performance modeling

Hardware-software co-design

Tools

ML compiler

Simulation tools

Job description

Role overview

Define the hardware architecture strategy for future AI computing in wearable, virtual reality, and augmented reality devices. The work spans AI compute and memory systems as well as camera and imaging pipelines for real-time perception, scene understanding, and mixed-reality experiences. The role sets long-range technical direction and guides decisions across hardware and software teams.

Responsibilities

• Develop multi-generation architecture plans for on-device AI inference and training across wearable and spatial computing devices.
• Evaluate system trade-offs across compute, memory hierarchy, interconnects, and power delivery for target workloads.
• Architect camera pipelines, including sensor interfaces, image signal processing, multi-camera synchronization, and depth sensing.
• Set requirements and performance targets for AI accelerators, image processors, systems-on-chip, and supporting subsystems.
• Build or guide performance models and simulations to assess designs against real AI and imaging workloads.
• Partner with silicon, firmware, camera, and machine learning teams to improve end-to-end performance and energy efficiency.
• Provide technical direction, resolve system bottlenecks, and communicate architecture decisions to engineering leaders and partners.
• Assess external technologies and suppliers to inform longer-term architecture plans.

Requirements

• At least 12 years of hardware systems architecture experience focused on AI, machine learning, imaging, or high-performance computing.
• Deep knowledge of camera pipelines, image signal processors, sensor integration, and end-to-end imaging system design.
• Experience defining system-on-chip or system-level architectures for AI workloads, including memory and interconnect design.
• Experience with real-time computer vision imaging systems, such as multi-camera setups, depth sensing, or visual-inertial odometry.
• Familiarity with hardware and software co-design for on-device AI and imaging, including ML compiler or image processor tuning workflows.
• Ability to develop performance models and evaluate architecture trade-offs through simulation or analytical methods.
• Track record of setting multi-year hardware roadmaps and influencing silicon strategy across engineering teams.
• Knowledge of custom silicon development, power- and area-constrained devices, computational photography, and emerging memory technologies.