AI Lead Architect for Chip Design

Socket.dev; San Jose (CA); On-site; USD 206,000 - 303,000; Full time

Job summary

Altera is seeking an AI Lead in HW Engineering to define and drive the company's AI strategy for chip design and to lead its deployment into design, verification, and implementation workflows. This senior IC design role emphasizes hands-on hardware/EDA expertise and the ability to act as a change agent across large engineering teams.

You will build an AI tooling stack, establish evaluation protocols, mentor engineers, and partner with CAD/IT to enable ML-ready telemetry and workflows.

Qualifications

• 12+ years of hands-on semiconductor hardware design experience.
• Proven experience applying AI/ML to design/verification workflows.
• Strong Python proficiency and ML tooling knowledge.
• Ability to lead initiatives without direct management authority.
• Excellent communication with senior stakeholders.

Responsibilities

• Define AI strategy for hardware design, verification, and implementation.
• Lead end-to-end deployment of AI-driven design tools into production flows.
• Build and own the AI tooling stack and evaluation harnesses.
• Establish benchmarking, versioning, monitoring, and retirement policies.
• Collaborate with design, verification, DFT, and EDA teams to integrate AI solutions.
• Engage with senior stakeholders and customers to communicate progress.

Skills

AI/ML for hardware design

Leadership without authority

Communication with executives

Python & ML tooling

Hardware/EDA credibility

Education

BS/MS/PhD in EE/CE/CS or related

Tools

EDA tooling

LLM tooling

Job description

Altera is seeking an AI Lead in HW Engineering to define and drive the company's AI strategy for chip design and to lead its deployment into design, verification, and implementation workflows. This senior IC design role emphasizes hands-on hardware/EDA expertise and the ability to act as a change agent across large engineering teams.

You will build an AI tooling stack, establish evaluation protocols, mentor engineers, and partner with CAD/IT to enable ML-ready telemetry and workflows.