AI Hardware Research Engineer — Hybrid, San Jose

TSMC - Taiwan Semiconductor Manufacturing Company Limited

California (MO)

Hybrid

USD 130,000 - 180,000

Full time

14 days+
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Job summary

TSMC Technology, Inc. (TTI) in San Jose is seeking an exceptional AI Hardware Research Engineer to drive breakthrough in AI hardware design, architecture, and algorithms.

You will join a team that shapes AI computing through high‑impact research and cross‑disciplinary collaboration in a hybrid work environment. Responsibilities include workload performance evaluation, benchmarking, guiding R&D directions, leveraging packaging and memory tech, and developing concepts to address scaling and

Qualifications

  • PhD in Electrical Engineering or Computer Science or related STEM field.
  • Recent Ph.D. graduate (0–2 years industry experience) with strong academic record.
  • Experience in modeling/simulation of AI hardware and systems; LLM algorithms and frameworks.

Responsibilities

  • Conduct workload-level performance evaluation and technology benchmarking for AI systems.
  • Provide strategic guidance to R&D on technology directions based on system evaluations.
  • Identify opportunities to leverage packaging and memory technologies within AI hardware architectures.
  • Develop concepts to address scalability and efficiency in next-generation AI hardware.

Skills

AI hardware modeling
LLM inference architectures
Accelerator architectures
Memory architectures
Packaging technologies

Education

PhD in Electrical Engineering or Computer Science

Job description

TSMC Technology, Inc. (TTI) in San Jose is seeking an exceptional AI Hardware Research Engineer to drive breakthrough in AI hardware design, architecture, and algorithms.

You will join a team that shapes AI computing through high‑impact research and cross‑disciplinary collaboration in a hybrid work environment. Responsibilities include workload performance evaluation, benchmarking, guiding R&D directions, leveraging packaging and memory tech, and developing concepts to address scaling and

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