AI-Driven SoC Design Intern

SK hynix memory solutions; Santa Clara (CA); On-site; USD 73,000 - 94,000; Full time

Job summary

SK hynix memory solutions in San Jose, CA, invites applications for a research internship in loop engineering. You will build or extend an automated AI-assisted co-design loop for SoC designs, using CHIA/Chisel/XLS, and run experiments to interpret design automation results.

The role involves defining a scoped research question, executing the loop, and documenting findings with a focus on reproducibility and reliability. Start date: Sept/Oct 2026, 40 hours/week, 6 months, on-site in San Jose.

Qualifications

• Progress toward a bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, computer science, or a related field.
• Coursework or project experience in loop engineering, computer architecture, digital design, VLSI, or electronic design automation.
• Fluency in Python, and comfort reading and changing an existing codebase.
• Ability to pose a small research question, keep a record of what changed, and explain the result.

Responsibilities

• Study how a design loop should be structured: steps, feedback, and how results drive the next iteration.
• Implement the loop with tools like Chisel and XLS and run simulations.
• Apply loop design to an SoC problem like microarchitectural exploration, RTL, or power/performance/area optimization.
• Compare loop designs on design point quality, search cost, and reproducibility.
• Make the loop rerunnable with clear interfaces, cached results, regression checks, and reports.

Skills

Python

Loop engineering

Computer architecture

Digital design

VLSI

Electronic design automation

Chisel

XLS

Verilog

SystemVerilog

Education

Bachelor’s/Master’s/Ph.D. in EE/CE/CS (in progress)

Tools

Chisel

XLS

Verilog

SystemVerilog

Job description

SK hynix memory solutions in San Jose, CA, invites applications for a research internship in loop engineering. You will build or extend an automated AI-assisted co-design loop for SoC designs, using CHIA/Chisel/XLS, and run experiments to interpret design automation results.

The role involves defining a scoped research question, executing the loop, and documenting findings with a focus on reproducibility and reliability. Start date: Sept/Oct 2026, 40 hours/week, 6 months, on-site in San Jose.