AI-Driven CAD Design Automation Engineer

Micron; Boise (ID); On-site; USD 110,000 - 150,000; Full time

Job summary

Micron Technology in Boise, Idaho is hiring a CAD Engineer to design, debug, and support AI assisted CAD tools and flows for CMOS design and verification. You will develop P-cells, scripts, and automation, collaborating with design, PI, and process teams to address workflow challenges and implement scalable layout methodologies.

The role requires a BS in a computer engineering or related field, 2+ years in CAD/VLSI, and experience with Cadence SKILL and Python/Perl.

Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, or a related field.
• 2+ years of experience in CAD, VLSI, or a related semiconductor engineering role.
• Experience programming in SKILL/Skill++ (Cadence), Python, and/or Perl.
• Experience with PDK development and/or validation and familiarity with Cadence EDA tools and flows.
• Experience with Linux/Unix environments, shell scripting, databases, and version control.
• Effective communication skills in a collaborative engineering environment.

Responsibilities

• Design, develop, and support AI assisted CAD software, EDA tools, flows, and methodologies for CMOS design and verification
• Debug, evaluate, and support in-house and commercial AI enabled EDA solutions in a production environment
• Develop P-cells, scripts, and automation for physical design, verification, optimization, and tapeout
• Collaborate closely with design, PI, and process teams to solve workflow and tool challenges, and to implement scalable layout methodologies aligned with PDK requirements
• Document processes and provide training and support for end users

Skills

CAD/VLSI experience

Linux/Unix + scripting

Communication

Education

Bachelor's degree in Computer Engineering, Computer Science, or related field

Tools

Cadence SKILL/Skill++

Python

Perl

Job description

Micron Technology in Boise, Idaho is hiring a CAD Engineer to design, debug, and support AI assisted CAD tools and flows for CMOS design and verification. You will develop P-cells, scripts, and automation, collaborating with design, PI, and process teams to address workflow challenges and implement scalable layout methodologies.

The role requires a BS in a computer engineering or related field, 2+ years in CAD/VLSI, and experience with Cadence SKILL and Python/Perl.