Analog Layout Automation Engineer

Apple, Inc.; Beaverton (OR); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. is seeking a highly skilled Analog Layout Automation Engineer in Beaverton, OR to help define the next generation of SOCs.

You will convert concepts into silicon, collaborate with circuit designers, and leverage AI-powered CAD tools to create high-performance analog and mixed-signal layouts. The role emphasizes automation, scripting, and data-driven design insights, with emphasis on LVS/DRC/ERC validation, device matching, low noise, and power; experience with Cadence tools and

Qualifications

• BS degree and at least 10 years of relevant industry experience.
• Experience designing analog and mixed-signal layouts in advanced CMOS/FinFET tech.
• Strong programming/scripting in Python, TCL, or Perl; layout automation
• Experience with AI/ML for layout optimization and data-driven design insights

Responsibilities

• Convert design concepts into silicon by collaborating with circuit designers and CAD tools.
• Review floor plans and analyze circuits for high-performance analog/mixed‑signal layouts.
• Run verification suites and resolve LVS/DRC/ERC issues.
• Develop scripts to automate layouts and workflows; apply AI/ML for optimization.
• Collaborate with cross-functional teams to deliver next‑gen SOCs.

Skills

Analog layout

Layout automation

Python

PyTorch

CAD tools

Data analysis

Cross-functional collaboration

Education

BS degree in Electrical Engineering or related field

Tools

Cadence Virtuoso (XL, EAD, APR)

Cadence Innovus

LVS/DRC/ERC tooling

Job description

Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems‑on‑chip (SOCs)! Our SOCs, featuring multi‑billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed‑Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency.

Description

As an Analog Layout Automation Engineer, you’ll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI‑powered, CAD tools to create high‑performance analog and mixed‑signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next‑generation SOCs. You’ll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data‑driven design insights.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience.

Preferred Qualifications

• Experience designing analog and mixed‑signal layouts in deep‑submicron CMOS and FinFET technologies.
• Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis.
• Solid understanding of supervised and self‑supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization.
• Hands‑on experience with PyTorch for model development and experimentation.
• Demonstrated ability to automate layout tasks, flows, and quality checks using scripting and CAD tools.
• Proven record in implementing high‑quality analog layouts with tight device matching, low noise, and low power consumption.
• Familiarity with failure‑prone circuit/layout structures, analog and DFM best practices, and the ability to diagnose and resolve layout‑related issues.
• Strong proficiency in custom and standard‑cell floor planning, hierarchical layout assembly, and physical integration.
• Understanding of image processing fundamentals, spatial representations, multi‑channel image handling, segmentation, and object detection concepts.
• Technical understanding of IR drop, RC delay, electromigration, self‑heating, coupling capacitance, and related reliability concerns.
• High proficiency in interpreting physical verification reports, including DRC, ERC, and LVS.
• Experience using advanced Cadence Virtuoso features (XL, EAD, APR, Constraint Manager), and familiarity with Cadence Innovus.
• Experience with CAD automation workflows and PCell creation.
• Excellent communication skills and the ability to work effectively with cross‑functional teams.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.