AI Accelerator Compiler Lead: Graph Lowering & Optimizations

Velaura AI, Inc.; Santa Clara (CA); Hybrid; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking an Accelerator Compiler Lead to own the compiler and model-lowering stack for its AI accelerator.

You will drive the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, IR, graph transformations, quantization integration, and profiling. The ideal candidate has built or shipped compiler infrastructure for ML accelerators, GPUs, DSPs, or other heterogeneous compute targets.

Qualifications

• Proven experience in compiler development for ML accelerators.
• Strong knowledge of ML model formats, IRs, and quantization.
• Proficient in C++ and Python; production-grade software experience.

Responsibilities

• Lead architecture and development of the AI accelerator compiler stack.
• Own model ingestion and graph lowering from PyTorch export flows, ONNX, TensorFlow Lite.
• Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
• Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
• Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.
• Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
• Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.
• Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.
• Establish compiler verification and regression strategy for graph transformations, IR lowering, numerical behavior, model accuracy, and performance.
• Hire, mentor, and lead a team of compiler and ML systems engineers.

Skills

Compiler development

ML graph compilers

Code generation

Accelerators

ML formats

Graph IRs

Operator lowering

Tensor layouts

Quantization

Runtime interfaces

C++

Python

Production-quality

Systems software

MLIR

LLVM

TVM

XLA

IREE

Glow

TensorRT

OpenVINO

Correctness risks

Graph rewrites

Mixed precision

Operator fusion

Lowering

Collaboration

Hardware architects

Firmware

Runtime engineers

Model integration

SQA

Team leadership

Architecture lead

Tools

MLIR

LLVM

TVM

XLA

IREE

Glow

TensorRT

OpenVINO

Job description

Velaura AI, Inc. is seeking an Accelerator Compiler Lead to own the compiler and model-lowering stack for its AI accelerator.

You will drive the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, IR, graph transformations, quantization integration, and profiling. The ideal candidate has built or shipped compiler infrastructure for ML accelerators, GPUs, DSPs, or other heterogeneous compute targets.