Advanced Packaging Photolithography Development Engineer

Intel Corporation; Hillsboro (OR); On-site; USD 134,000 - 189,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Job summary

Intel seeks a Lithography Process Development Engineer to drive advanced packaging lithography, including hybrid bonding, in Hillsboro, OR. You will partner with process integration, equipment, metrology, and design teams to enable high interconnect density and yield.

The role focuses on developing and optimizing photolithography processes for backend applications, tooling integration, APC control, and defect-driven yield improvements, with a career in a cutting-edge packaging environment.

Qualifications

• Hands-on lithography process development experience with i-line, KrF or ArF lithography process development in a semiconductor fab.
• Hands-on experience with photoresist process development, including coat/bake/develop optimization, resist profile engineering, and process window characterization.
• Strong understanding of optical lithography fundamentals: aerial image formation, resist chemistry, focus-exposure matrix (FEM), depth of focus (DOF), and exposure latitude (EL).
• Proficiency in SPC and DOE principles.

Responsibilities

• Qualify scanner/stepper platforms and Track system for backend and hybrid bonding lithography applications.
• Develop, characterize, and optimize photolithography processes for back-end applications, including Cu damascene pad patterning, dielectric via and trench lithography, bonding interface layer patterning, and alignment mark / overlay target design and optimization.
• Evaluate and implement underlayer stacks to address topography challenges inherent in far backend and packaging substrates.
• Develop and optimize overlay metrology and control strategies critical for advanced packaging nodes.
• Implement APC including run-to-run and lot-to-lot overlay feedback/feedforward control loops.
• Work with integration and other modules to develop fully integrated process flows, ensuring lithography compatibility with upstream and downstream steps.
• Support yield learning by defect analysis and corrective actions for lithography-related yield detractors.
• Contribute to technology roadmap planning for next-generation node and engage with suppliers to evaluate next-generation tools and materials.

Skills

Lithography process development

i-line KrF ArF lithography

Photoresist process development

Optical lithography fundamentals

SPC & DOE

Root cause analysis

Education

Master’s degree in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Electrical Engineering, Physics, Chemistry, or related fields

PhD degree in the same fields

Tools

CDSEM

OCD/Scatterometry

Job description

Job Details:

Job Description:

We are seeking a highly skilled and motivated Lithography Process Development Engineer to join our Advanced Packaging Technology Development team. In this role, you will be driving lithography process development at the forefront of next-generation semiconductor packaging technology, including hybrid bonding applications. You will work in a dynamic, cross-functional environment collaborating with process integration, equipment, metrology, and design teams to enable industry-leading interconnect density and yield.

Key Responsibilities

• Qualify scanner/stepper platforms and Track system for backend and hybrid bonding lithography applications
• Develop, characterize, and optimize photolithography processes for back-end applications, including Cu damascene pad patterning, dielectric via and trench lithography, bonding interface layer patterning, and alignment mark / overlay target design and optimization
• Evaluate and implement underlayer stacks to address topography challenges inherent in far backend and packaging substrates
• Develop and optimize overlay metrology and control strategies critical for advanced packaging nodes
• Implement advanced process control (APC) including run-to-run (R2R) and lot-to-lot overlay feedback/feedforward control loops
• Work closely with integration and other modules to develop fully integrated process flows, ensuring lithography compatibility with upstream and downstream process steps
• Support yield learning by performing systematic defect analysis, root cause investigation, and implementing corrective actions for lithography-related yield detractors
• Contribute to technology roadmap planning for next-generation node and engage with equipment and material suppliers to evaluate next-generation tools and materials

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Master’s degree in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Electrical Engineering, Physics, Chemistry, or related fields with 3+ years of relevant experience
• PhD degree in the same fields with 2+ years of relevant experience

Experience listed above should be a combination of the following:

• Hands-on lithography process development experience with i-line, KrF or ArF lithography process development in a semiconductor fab
• Hands-on experience with photoresist process development, including coat/bake/develop optimization, resist profile engineering, and process window characterization
• Strong understanding of optical lithography fundamentals: aerial image formation, resist chemistry, focus-exposure matrix (FEM), depth of focus (DOF), and exposure latitude (EL)
• Proficiency in Statistical Process Control (SPC) and Design of Experiments (DOE) principles.

Preferred Qualifications

• Strong analytical and problem-solving skills with ability to perform systematic root cause analysis on complex, multi-variable process issues
• Experience with packaging processes, equipment automation development, or project management in technology development.
• Experience in advanced packaging lithography environments (Foveros, Foveros Direct, fan-out WLP, 2.5D/3D IC, CoWoS, SoIC, or equivalent)
• Experience with overlay metrology and control, and familiarity with CDSEM and OCD/scatterometry for process monitoring and control

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $133,800.00-188,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.