Test Engineer – ATE (Digital, PMIC, RF & Mixed Signal)

VY SYSTEMS PTE. LTD.; Singapore; On-site; SGD 48,000 - 72,000; Full time

Job summary

VY SYSTEMS PTE. LTD. in Singapore invites applications for a Test Engineer role focused on Digital, PMIC, RF and Mixed Signal product test development.

You will collaborate with design engineers on silicon debug, characterization, test program bring-up and production release activities. You will debug digital vectors (JTAG/SCAN/ATPG/Functional/Mbist), characterize devices across PVT, and contribute to yield improvement and test time reduction while working closely with cross‑functional teams in

Qualifications

• Diploma or Bachelors in Electronics/Electrical Engineering.
• 2-4 years of relevant Test Engineering experience preferred.
• Hands-on experience with Teradyne Ultra Flex or Advantest 93K ATE is an advantage.
• Good knowledge of analog and digital electronics.
• Strong analytical and problem-solving skills; hands-on lab work required.
• Excellent verbal and written communication; able to work independently.

Responsibilities

• Test program development for Digital, PMIC, RF & Mixed Signal products on ATE (Advantest 93k, SmarTest 7/8; Teradyne UFLEX).
• Collaborate with design engineers on first silicon debug, device characterization, test program bring-up, and production release activities.
• Debug digital vectors (JTAG/SCAN/ATPG/Functional/Mbist) and characterize devices across PVT.
• Characterize Mixed Signal IP (ADC, DAC, PLL, etc.).
• Contribute to test program hand-off, production release, yield improvement and test time reduction.
• Collaborate with Product, Design, Quality, and Foundry Engineering teams.

Skills

Test program development

Lab work

Analytical thinking

Hands-on debugging

Education

Diploma/ Degree in Electronics or Electrical Engineering

Tools

Advantest 93K ATE

Teradyne Ultra Flex

JTAG/SCAN/ATPG

Job description

Roles & Responsibilities

• Test program development for Digital, PMIC, RF & Mixed Signal products on ATE (primarily on Advantest 93k - SmarTest 7, SmarTest 8 / Teradyne UFLEX).

• Work closely with the design engineers on the first silicon debug, device characterization, test program bring up and production release activities.

• Debug of digital vectors (JTAG/SCAN/ATPG / Functional / Mbist) and Device characterization across PVT (Process, Voltage and Temperature).

• Understanding and experience in characterization of Mixed Signal IP (ADC, DAC, PLL and etc.).

• Involve on test program hand o, production release, yield improvement and test time reduction.

• High level of collaboration and interaction with different Product Engineering, Design Engineering, Quality Engineering, and Foundry Engineering teams.

Job Requirements

• Graduates from Diploma/ Degree in Electronics / Electrical Engineering.

• Minimum Minimum 2-4 years of relevant experience on the Test Engineering is preferred.

• Hands on experience on Teradyne Ultra Flex or Advantest 93K ATE’s is added advantage.

• Good Knowledge of analog and digital electronics is desired.

• Strong analytical and problem solving ability with desire to perform hands‑on work within a lab environment is a must.

• Very strong verbal and written communication skills and able to work independently.