Synthesis & Timing Signoff Engineer (Low-Power)

ByteDance; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

ByteDance’s Silicon Platform Team seeks an experienced IC designer to drive logic synthesis, timing signoff, and low-power implementation across chip projects. You will collaborate with front-end and backend teams to explore architectures and deliver optimized RTL-to-GDSII flows using industry-standard EDA tools.

The role requires 3+ years in IC design, strong Verilog/SystemVerilog skills, and proficiency with synthesis, DFT, and power optimization methodologies.

Qualifications

• 3+ years of experience in IC design with a focus on SDC, synthesis, timing signoff, low-power implementation, and power optimization.
• Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.

Responsibilities

• Perform logic synthesis and design optimization for architectures and RTLs.
• Timing constrains (SDC) preparation and tuning, and conduct hierarchical/full-chip STA signoff and timing closure.
• Implement low-power design techniques and constraints (UPF, clock gating, power gating, dynamic voltage scaling).
• Formal verification & equivalence checking using formal verification tools (Conformal, Formality).
• Work with front-end engineers for architectural exploration and planning.
• Work with backend engineers on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Skills

Verilog

SystemVerilog

RTL-to-GDSII flow

EDA tools

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Fusion Compiler

Genus/Innovus+

PrimeTime/Tempus

Formality

Conformal LP

Job description

ByteDance’s Silicon Platform Team seeks an experienced IC designer to drive logic synthesis, timing signoff, and low-power implementation across chip projects. You will collaborate with front-end and backend teams to explore architectures and deliver optimized RTL-to-GDSII flows using industry-standard EDA tools.

The role requires 3+ years in IC design, strong Verilog/SystemVerilog skills, and proficiency with synthesis, DFT, and power optimization methodologies.