Synthesis Methodology Architect – AI SoC Flows

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd is seeking an experienced Synthesis Methodology Engineer to own RTL synthesis methodologies across AI SoC projects. You will develop, maintain, and optimize synthesis flows, evaluate new EDA tools, and enable efficient implementation across technology nodes.

You will collaborate with Design, Backend, CAD, and EDA vendors to improve productivity and design quality, focusing on sign-off readiness, timing optimization, and automation through Tcl/Python

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 5+ years of ASIC/SoC RTL synthesis or synthesis methodology experience.
• Hands-on experience with Synopsys Design Compiler.
• Familiarity with sign-off tools like PrimeTime, Formality, VC SpyGlass, and VCLP.
• Experience with RTL synthesis, timing optimization, and ASIC implementation flow.
• Proficiency in Tcl, Shell, or Python scripting for automation.

Responsibilities

• Own, develop, maintain, and optimize RTL synthesis flows across AI/SoC projects.
• Evaluate new EDA tools and enable efficient implementation across nodes.
• Collaborate with Design, CAD, Backend, and EDA vendors to improve productivity.
• Ensure design convergence and sign-off readiness using PrimeTime and related tools.
• Migrate technology nodes and update libraries as required.

Skills

RTL synthesis expertise

Automation & scripting

Analytical/problem-solving

Effective communication

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related

Tools

Synopsys Design Compiler

PrimeTime

Formality

VC SpyGlass

VCLP

Fusion Compiler

Cadence Genus

Job description

Black Sesame Technologies (Singapore) Pte Ltd is seeking an experienced Synthesis Methodology Engineer to own RTL synthesis methodologies across AI SoC projects. You will develop, maintain, and optimize synthesis flows, evaluate new EDA tools, and enable efficient implementation across technology nodes.

You will collaborate with Design, Backend, CAD, and EDA vendors to improve productivity and design quality, focusing on sign-off readiness, timing optimization, and automation through Tcl/Python