Staff Digital IC Design Engineer — PMIC/ADC/DAC

Analog Devices, Inc.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Analog Devices, Inc. in Singapore is seeking a Staff Engineer for Digital Design Engineering to develop next-generation PMICs for portable consumer applications. You will lead RTL design, architecture, and verification across cross-disciplinary teams of analog, mixed-signal, and system engineers.

The role emphasizes power-management ICs, block- and chip-level design, and close collaboration with cross-functional teams. Travel is expected, and a strong background in RTL and EDA flows is required.

Qualifications

• MSEE or Ph.D EE with 7+ years' experience as a digital/mixed-signal IC designer.
• Strong hands-on RTL design, digital architecture, and mixed-signal integration.
• Solid understanding of verification methodologies and flows; block- and system-level.
• Familiarity with EDA flows and scripting (Python, Tcl, Perl).
• Excellent communication skills; some travel expected.

Responsibilities

• Participate in the design and development of mixed-signal IC products.
• Perform block-level and chip-level RTL design and implementation.
• Design digital signal processing blocks based on algorithms and translate requirements into digital implementations.
• Define digital architectures per product specs.
• Participate in block- and chip-level verification activities.
• Contribute to block- and system-level digital/mixed-signal testbench development.

Skills

RTL design

digital architecture

mixed-signal integration

Python

Tcl

Perl

communication skills

Education

MSEE or Ph.D EE

Tools

EDA tools (Synthesis/STA/Verification)

Synopsys Cadence Mentor

Job description

Analog Devices, Inc. in Singapore is seeking a Staff Engineer for Digital Design Engineering to develop next-generation PMICs for portable consumer applications. You will lead RTL design, architecture, and verification across cross-disciplinary teams of analog, mixed-signal, and system engineers.

The role emphasizes power-management ICs, block- and chip-level design, and close collaboration with cross-functional teams. Travel is expected, and a strong background in RTL and EDA flows is required.