SG Analog/Mixed-Signal Verification Engineer

TetraMem - Accelerate The World; Singapore; On-site; SGD 80,000 - 180,000; Full time

Job summary

TetraMem - Accelerate The World is seeking a seasoned IC verification engineer in Singapore to lead mixed-signal verification efforts. You will develop verification plans, create testbenches, and verify analog/mixed-signal circuits for functionality, performance, and reliability.

You will review results with design teams, collaborate with layout, and drive sign-off for tapeout. Proficiency in Verilog/VHDL, waveform viewers, and scripting (Python/Perl/C) is essential; strong communication and

Qualifications

• BS EE degree with 5+ years in IC verification.
• Strong analog/mixed-signal verification knowledge.
• Experience writing test plans and presenting results.
• Familiarity with simulators, waveform viewers, and coverage.
• Proficient in Perl, Python, or C for scripting.
• Excellent debugging and teamwork skills.

Responsibilities

• Develop and implement mixed-signal verification plans.
• Design verification testbenches and tests.
• Verify mixed-signal circuits for functionality and performance.
• Review results and provide feedback to design teams.
• Collaborate with design and layout teams to resolve issues.
• Sign-off designs for tapeout.

Skills

Analog/Mixed-signal

Verification principles

Scripting: Perl/Python/C

Communication skills

Debugging

Teamwork

Education

Bachelor of Science in Electrical Engineering

Tools

Verilog

VHDL

Waveform viewers

Testbench development

Job description

Responsibilities

• Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications
• Design and develop verification testbenches using industry-standard verification languages and methodologies
• Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability
• Review and analyze verification results, and provide feedback to design teams
• Collaborate with design and layout teams to identify and resolve design issues
• Develop new verification methodologies, tools, and techniques, ensuring scalability and portability
• Sign-off mixed signal designs in preparation for tapeout

Requirements

• B.S. EE and 5+ years of relevant industry experience or equivalent
• Strong understanding of analog and mixed-signal circuit design and verification principles
• Ability to write test plans, present results, and communicate clearly with multi-functional teams
• Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, simulation time optimization, and coverage collection
• Have good programming skills and can write efficient programs or scripts in Perl, Python, and/or C
• Excellent debugging, problem-solving and analytical skills
• Strong communication and teamwork skills
• Familiarity with analog behavioral models is a plus

Salary Range: S$80,000 - S$180,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.

TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.