Senior Probe Engineering Lead - Silicon Test & Yield

Micron Memory Malaysia Sdn Bhd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Micron Technology, Inc. in Singapore seeks a Senior/Staff STPG Engineer Product Engineering to own probe coverage and drive silicon learning from pre‑silicon to high‑volume manufacturing.

You will collaborate with Design, DFT, DV, Process Integration, Backend Test, and Reliability teams to ensure scalable, manufacturable probe solutions aligned with downstream test and customer requirements. The role emphasizes defining probe limits, gating test cost, and enabling efficient yield ramp through

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus) or related field.
• Strong fundamentals in semiconductor devices, wafer test, and product engineering.
• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.
• Strong analytical skills and ability to drive structured root‑cause analysis.
• Effective communication skills and ability to work across global, cross‑functional teams.

Responsibilities

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met.
• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.
• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.
• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.
• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.
• Define probe coverage intent early and ensure continuity from design features through probe and downstream test.
• Support first silicon bring‑up using engineering probe platforms and lab‑based characterization setups.
• Perform silicon and device‑level characterization to inform probe limits and screening strategy.
• Correlate early silicon behavior with probe results to validate coverage intent and identify gaps.
• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.
• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.
• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams.
• Drive test efficiency improvements through coverage right‑sizing and flow optimization.
• Support wafer‑level speed activities as part of broader probe optimization efforts.
• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.
• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

Skills

Semiconductor fundamentals

Silicon learning

DFT intent

Design‑to‑manufacturing integration

Analytical skills

Communication skills

Education

Bachelors in Electrical/Electronics Engineering

Masters in Electrical/Electronics Engineering

PhD in related field

Job description

Micron Technology, Inc. in Singapore seeks a Senior/Staff STPG Engineer Product Engineering to own probe coverage and drive silicon learning from pre‑silicon to high‑volume manufacturing.

You will collaborate with Design, DFT, DV, Process Integration, Backend Test, and Reliability teams to ensure scalable, manufacturable probe solutions aligned with downstream test and customer requirements. The role emphasizes defining probe limits, gating test cost, and enabling efficient yield ramp through