Senior Integration Engineer, Yield & Defect Reduction

Vanguard International Semiconductor Corporation; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

Vanguard International Semiconductor Corporation in Singapore seeks an experienced engineer to drive defect reduction and yield improvement across front-end wafer manufacturing. You will supervise YE Associate Engineers and train staff on defect sources, recipes, and inline failure analysis, ensuring quality and adherence to SOPs.

The role requires 2–6 years in high-volume electronics fab, strong collaboration, and a proactive approach to EHSS policies.

Qualifications

• Master’s or bachelor’s degree in a relevant engineering field with strong analytical skills.
• 2–6 years of fab experience in high-volume electronics manufacturing (front-end SEM).
• Experience in defect analysis and yield improvement is required.
• Good interpersonal and leadership abilities with teamwork mindset.
• Commitment to EHSS policies and safe workplace practices.

Responsibilities

• Liaise with module engineers to control defect excursions.
• Drive defect reduction and yield improvement activities.
• Supervise YE Associate Engineers and wafer tech operators.
• Train YE engineers on recipe creation and defect knowledge.
• Maintain SOP/OCAP and participate in audits.
• Operate inspection tools (FIB/SEM/EDX/OM) for inline failure analysis.
• Create recipes in Brightfield and Darkfield defect inspection tools.
• Prepare reports on defect sources and weekly performance.
• Build defect source library and track tool/chamber metrics.
• Conduct weekly defect performance reviews and optimization activities.
• Collaborate with process engineers across modules to troubleshoot defects.
• Support low yield investigations with cross-functional teams.
• Automate daily troubleshooting workflows to speed up the team.

Skills

Defect analysis

Yield enhancement

Leadership

Teamwork

Communication

Education

Masters / Degree in Electrical/Electronic Engineering

Material Science

Chemical Engineering

Physics

Tools

FIB/SEM/EDX/OM

Brightfield

Darkfield

Defect inspection tool

Job description

Vanguard International Semiconductor Corporation in Singapore seeks an experienced engineer to drive defect reduction and yield improvement across front-end wafer manufacturing. You will supervise YE Associate Engineers and train staff on defect sources, recipes, and inline failure analysis, ensuring quality and adherence to SOPs.

The role requires 2–6 years in high-volume electronics fab, strong collaboration, and a proactive approach to EHSS policies.