Senior Yield Defect & Integration Engineer

Vanguard International Semiconductor Corporation (VIS)

Singapore

On-site

SGD 85,000 - 120,000

Full time

14 days+

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Job summary

Vanguard International Semiconductor Corporation (VIS) in Singapore is seeking an experienced engineer to supervise YDD associate engineers and wafer tech operators ensuring smooth 24/7 inline shift operation.

You will train and certify associates on recipe creation, defect source knowledge, and participate in internal/external audits while operating FIB/SEM/EDX for inline failure analysis and developing defect source libraries.

Qualifications

Masters or Bachelor degree in Electrical / Electronics / Chemical / Microelectronics Engineering.
5-8 years of relevant work experience in high volume manufacturing of electronics components.
Experience in defect analysis and yield enhancement is preferred.
Excellent interpersonal and communication skills with leadership capability.
Strong analytical skills and ability to work under pressure in a fast-paced environment.

Responsibilities

Supervise YDD Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation.
Train and certify DO Associate Engineers on recipe creation and defect source knowledge.
Maintain and enhance internal SOP/CAS and involve in internal/external audit.
Operate FIB/SEM/EDX for inline failure analysis.
Operate and create recipes in Brightfield, Darkfield and other YDD tools.
Maintain and housekeeping Brightfield, Darkfield and recipes of other YDD tools.
Perform partition analysis on defect source and detailed reports on issues.
Build and develop defect source library and tool’s defect source fingerprinting.
Track inline defect performance by layer/process tool/chamber on weekly basis.
Perform defect characterization by process tools.
Continuous improvement activities on defect reductions with Modules / vendors / equipment team.
Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities.
Provide scan support in low yield investigation & co-work with PI/YE/PE on technology & device specific yield enhancement activities.
Automate daily activities to improve troubleshooting speed of team.
Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems.