Memory IC Layout Engineer — Cadence & Verification Expert

Broadcom; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Broadcom is seeking a Layout Engineer in Singapore to contribute to memory, I/O, and standard cell layouts within the Library Group of the Central Engineering Group.

The role requires 2–3 years of IC layout experience, strong Cadence layout and verification tool skills (Calibre, Hercules), and familiarity with submicron nodes from 16nm down to 1.4nm. Analog layout experience is a plus.

Qualifications

• 2–3 years of IC layout experience.
• Strong memory, I/O, and standard cell layout experience.
• Experience with submicron nodes (16nm to 1.4nm and below).
• LVS/DRC/ERC and reliability checks experience.
• Familiarity with advanced process rules and layout guidelines.

Responsibilities

• Understand and apply layout guidelines for standard cells, I/O, and memories.
• Plan schedules and perform floor-planning for layouts.
• Deliver quality layout and verification within schedule with minimal supervision for experienced engineers.
• Adapt quickly to new methodologies and communicate effectively with the library team.

Skills

Cadence layout

Cadence schematic capture

CALIBRE

Hercules verification

Memory layout design

Digital (standard cell, memory, I/O)

Analog layout

Floor-planning

Chip integration

VIRTUOSO

SKILL programming

Scripting

Memory topology

Memory compiler

Teamwork

Tools

Cadence Virtuoso XL/VXL/EXL

CALIBRE

Job description

Broadcom is seeking a Layout Engineer in Singapore to contribute to memory, I/O, and standard cell layouts within the Library Group of the Central Engineering Group.

The role requires 2–3 years of IC layout experience, strong Cadence layout and verification tool skills (Calibre, Hercules), and familiarity with submicron nodes from 16nm down to 1.4nm. Analog layout experience is a plus.